llvm::PPCISD Namespace Reference

Enumerations
enum	NodeType {   FIRST_NUMBER = ISD::BUILTIN_OP_END, FSEL, FCFID, FCTIDZ,   FCTIWZ, STFIWX, VMADDFP, VNMSUBFP,   VPERM, Hi, Lo, DYNALLOC,   GlobalBaseReg, SRL, SRA, SHL,   EXTSW_32, STD_32, CALL_Macho, CALL_ELF,   MTCTR, BCTRL_Macho, BCTRL_ELF, RET_FLAG,   MFCR, VCMP, VCMPo, COND_BRANCH,   STBRX, LBRX, MFFS, MTFSB0,   MTFSB1, FADDRTZ, MTFSF, LARX,   STCX, TAILCALL, TC_RETURN }

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Enumeration Type Documentation

enum llvm::PPCISD::NodeType

Enumerator:

FIRST_NUMBER
FSEL	FSEL - Traditional three-operand fsel node.
FCFID	FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP representation of the integer that was temporarily in the f64 operand.
FCTIDZ	FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value containing the integer representation of that FP value.
FCTIWZ
STFIWX	STFIWX - The STFIWX instruction. The first operand is an input token chain, then an f64 value to store, then an address to store it to, then a SRCVALUE for the address.
VMADDFP
VNMSUBFP
VPERM	VPERM - The PPC VPERM Instruction.
Hi	Hi/Lo - These represent the high and low 16-bit parts of a global address respectively. These nodes have two operands, the first of which must be a TargetGlobalAddress, and the second of which must be a Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', though these are usually folded into other nodes.
Lo
DYNALLOC	OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an allocation on the stack.
GlobalBaseReg	GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry, used for PIC code.
SRL	These nodes represent the 32-bit PPC shifts that operate on 6-bit shift amounts. These nodes are generated by the multi-precision shift code.
SRA
SHL
EXTSW_32	EXTSW_32 - This is the EXTSW instruction for use with "32-bit" registers.
STD_32	STD_32 - This is the STD instruction for use with "32-bit" registers.
CALL_Macho	CALL - A direct function call.
CALL_ELF
MTCTR	CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
BCTRL_Macho	CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
BCTRL_ELF
RET_FLAG	Return with a flag operand, matched by 'blr'.
MFCR	R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. This copies the bits corresponding to the specified CRREG into the resultant GPR. Bits corresponding to other CR regs are undefined.
VCMP	RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions. For lack of better number, we use the opcode number encoding for the OPC field to identify the compare. For example, 838 is VCMPGTSH.
VCMPo	RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the altivec VCMP*o instructions. For lack of better number, we use the opcode number encoding for the OPC field to identify the compare. For example, 838 is VCMPGTSH.
COND_BRANCH	CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo instruction. CRRC is the condition register to branch on, OPC is the branch opcode to use (e.g. PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is an optional input flag argument.
STBRX	CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a byte-swapping store instruction. It byte-swaps the low "Type" bits of the GPRC input, then stores it through Ptr. Type can be either i16 or i32.
LBRX	GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a byte-swapping load instruction. It loads "Type" bits, byte swaps it, then puts it in the bottom bits of the GPRC. TYPE can be either i16 or i32.
MFFS	OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the register.
MTFSB0	OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
MTFSB1	OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
FADDRTZ	F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with rounding towards zero. It has flags added so it won't move past the FPSCR-setting instructions.
MTFSF	MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
LARX	LARX = This corresponds to PPC l{w|d}arx instrcution: load and reserve indexed. This is used to implement atomic operations.
STCX	STCX = This corresponds to PPC stcx. instrcution: store conditional indexed. This is used to implement atomic operations.
TAILCALL	TAILCALL - Indicates a tail call should be taken.
TC_RETURN	TC_RETURN - A tail call return. operand #0 chain operand #1 callee (register or absolute) operand #2 stack adjustment operand #3 optional in flag

Definition at line 25 of file PPCISelLowering.h.