llvm::PPC Namespace Reference

Define some predicates that are used for node matching. More...

Enumerations

enum Predicate {
  PRED_ALWAYS = (0 << 5) | 20, PRED_LT = (0 << 5) | 12, PRED_LE = (1 << 5) | 4, PRED_EQ = (2 << 5) | 12,
  PRED_GE = (0 << 5) | 4, PRED_GT = (1 << 5) | 12, PRED_NE = (2 << 5) | 4, PRED_UN = (3 << 5) | 12,
  PRED_NU = (3 << 5) | 4
}

Predicate - These are "(BI << 5) | BO" for various predicates. More...

enum RelocationType {
  reloc_vanilla, reloc_pcrel_bx, reloc_pcrel_bcx, reloc_absolute_high,
  reloc_absolute_low, reloc_absolute_low_ix
}

enum {
  DIR_NONE, DIR_32, DIR_601, DIR_602,
  DIR_603, DIR_7400, DIR_750, DIR_970,
  DIR_64
}

Functions

bool isVPKUHUMShuffleMask (SDNode *N, bool isUnary)

bool isVPKUWUMShuffleMask (SDNode *N, bool isUnary)

bool isVMRGLShuffleMask (SDNode *N, unsigned UnitSize, bool isUnary)

bool isVMRGHShuffleMask (SDNode *N, unsigned UnitSize, bool isUnary)

int isVSLDOIShuffleMask (SDNode *N, bool isUnary)

bool isSplatShuffleMask (SDNode *N, unsigned EltSize)

bool isAllNegativeZeroVector (SDNode *N)

unsigned getVSPLTImmediate (SDNode *N, unsigned EltSize)

SDValue get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG)

Predicate InvertPredicate (Predicate Opcode)

Invert the specified predicate. != -> ==, < -> >=.

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

anonymous enum

Enumerator:

DIR_NONE
DIR_32
DIR_601
DIR_602
DIR_603
DIR_7400
DIR_750
DIR_970
DIR_64

Definition at line 29 of file PPCSubtarget.h.

enum llvm::PPC::Predicate

Predicate - These are "(BI << 5) | BO" for various predicates.

Enumerator:

PRED_ALWAYS
PRED_LT
PRED_LE
PRED_EQ
PRED_GE
PRED_GT
PRED_NE
PRED_UN
PRED_NU

Definition at line 22 of file PPCPredicates.h.

enum llvm::PPC::RelocationType

Enumerator:

reloc_vanilla
reloc_pcrel_bx
reloc_pcrel_bcx
reloc_absolute_high
reloc_absolute_low
reloc_absolute_low_ix

Definition at line 27 of file PPCRelocations.h.

Function Documentation

SDValue llvm::PPC::get_VSPLTI_elt	(	SDNode *	N,
		unsigned	ByteSize,
		SelectionDAG &	DAG
	)

get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted. The ByteSize field indicates the number of bytes of each element [124] -> [bhw].

Definition at line 616 of file PPCISelLowering.cpp.

References llvm::MVT::f32, llvm::FloatToBits(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::ISD::UNDEF, and Val.

unsigned llvm::PPC::getVSPLTImmediate	(	SDNode *	N,
		unsigned	EltSize
	)

getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask.

Definition at line 607 of file PPCISelLowering.cpp.

References llvm::SDNode::getOperand(), and isSplatShuffleMask().

PPC::Predicate llvm::PPC::InvertPredicate ( PPC::Predicate Opcode )

Invert the specified predicate. != -> ==, < -> >=.

Definition at line 18 of file PPCPredicates.cpp.

References PRED_EQ, PRED_GE, PRED_GT, PRED_LE, PRED_LT, PRED_NE, PRED_NU, and PRED_UN.

Referenced by llvm::PPCInstrInfo::ReverseBranchCondition().

bool llvm::PPC::isAllNegativeZeroVector ( SDNode * N )

isAllNegativeZeroVector - Returns true if all elements of build_vector are -0.0.

Definition at line 597 of file PPCISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), and isSplatShuffleMask().

bool llvm::PPC::isSplatShuffleMask	(	SDNode *	N,
		unsigned	EltSize
	)

isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.

Definition at line 558 of file PPCISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

Referenced by getVSPLTImmediate(), and isAllNegativeZeroVector().

bool llvm::PPC::isVMRGHShuffleMask	(	SDNode *	N,
		unsigned	UnitSize,
		bool	isUnary
	)

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).

Definition at line 515 of file PPCISelLowering.cpp.

References isVMerge().

bool llvm::PPC::isVMRGLShuffleMask	(	SDNode *	N,
		unsigned	UnitSize,
		bool	isUnary
	)

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).

Definition at line 507 of file PPCISelLowering.cpp.

References isVMerge().

bool llvm::PPC::isVPKUHUMShuffleMask	(	SDNode *	N,
		bool	isUnary
	)

isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.

Definition at line 452 of file PPCISelLowering.cpp.

References llvm::SDNode::getOperand(), and isConstantOrUndef().

bool llvm::PPC::isVPKUWUMShuffleMask	(	SDNode *	N,
		bool	isUnary
	)

isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.

Definition at line 468 of file PPCISelLowering.cpp.

References llvm::SDNode::getOperand(), and isConstantOrUndef().

int llvm::PPC::isVSLDOIShuffleMask	(	SDNode *	N,
		bool	isUnary
	)

isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.

Definition at line 524 of file PPCISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), isConstantOrUndef(), and llvm::ISD::UNDEF.


Enumerations
enum	Predicate { PRED_ALWAYS = (0 << 5) \| 20, PRED_LT = (0 << 5) \| 12, PRED_LE = (1 << 5) \| 4, PRED_EQ = (2 << 5) \| 12, PRED_GE = (0 << 5) \| 4, PRED_GT = (1 << 5) \| 12, PRED_NE = (2 << 5) \| 4, PRED_UN = (3 << 5) \| 12, PRED_NU = (3 << 5) \| 4 }
	Predicate - These are "(BI << 5) \| BO" for various predicates. More...
enum	RelocationType { reloc_vanilla, reloc_pcrel_bx, reloc_pcrel_bcx, reloc_absolute_high, reloc_absolute_low, reloc_absolute_low_ix }
enum	{ DIR_NONE, DIR_32, DIR_601, DIR_602, DIR_603, DIR_7400, DIR_750, DIR_970, DIR_64 }
Functions
bool	isVPKUHUMShuffleMask (SDNode *N, bool isUnary)
bool	isVPKUWUMShuffleMask (SDNode *N, bool isUnary)
bool	isVMRGLShuffleMask (SDNode *N, unsigned UnitSize, bool isUnary)
bool	isVMRGHShuffleMask (SDNode *N, unsigned UnitSize, bool isUnary)
int	isVSLDOIShuffleMask (SDNode *N, bool isUnary)
bool	isSplatShuffleMask (SDNode *N, unsigned EltSize)
bool	isAllNegativeZeroVector (SDNode *N)
unsigned	getVSPLTImmediate (SDNode *N, unsigned EltSize)
SDValue	get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
Predicate	InvertPredicate (Predicate Opcode)
	Invert the specified predicate. != -> ==, < -> >=.