llvm::X86InstrInfo Class Reference
#include <X86InstrInfo.h>
Detailed Description
Definition at line 263 of file X86InstrInfo.h.
Constructor & Destructor Documentation
| X86InstrInfo::X86InstrInfo | ( | X86TargetMachine & | tm | ) | [explicit] |
Definition at line 49 of file X86InstrInfo.cpp.
References llvm::array_lengthof(), llvm::SmallVectorImpl< T >::empty(), llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::insert(), and llvm::SmallVectorImpl< T >::push_back().
Member Function Documentation
| virtual const X86RegisterInfo& llvm::X86InstrInfo::getRegisterInfo | ( | ) | const [inline, virtual] |
getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 286 of file X86InstrInfo.h.
Referenced by llvm::X86TargetMachine::getRegisterInfo().
| bool X86InstrInfo::isMoveInstr | ( | const MachineInstr & | MI, | |
| unsigned & | sourceReg, | |||
| unsigned & | destReg | |||
| ) | const [virtual] |
Return true if the instruction is a register to register move and leave the source and dest operands in the passed parameters.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 660 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().
| unsigned X86InstrInfo::isLoadFromStackSlot | ( | const MachineInstr * | MI, | |
| int & | FrameIndex | |||
| ) | const [virtual] |
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 700 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
| unsigned X86InstrInfo::isStoreToStackSlot | ( | const MachineInstr * | MI, | |
| int & | FrameIndex | |||
| ) | const [virtual] |
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 730 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
| bool X86InstrInfo::isReallyTriviallyReMaterializable | ( | const MachineInstr * | MI | ) | const [virtual] |
isReallyTriviallyReMaterializable - For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this function tests whether the instruction itself is actually trivially rematerializable, considering its operands. This is used for targets that have instructions that are only trivially rematerializable for specific uses. This predicate must return false if the instruction has any side effects other than producing a value, or if it requres any address registers that are not always available.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 784 of file X86InstrInfo.cpp.
References BaseReg, llvm::MachineRegisterInfo::def_begin(), llvm::MachineRegisterInfo::def_end(), E, llvm::MachineOperand::getGlobal(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), I, llvm::MachineOperand::isCPI(), llvm::MachineOperand::isGlobal(), isGVStub(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), MF, MRI, regIsPICBase(), and ReMatPICStubLoad.
| void X86InstrInfo::reMaterialize | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | DestReg, | |||
| const MachineInstr * | Orig | |||
| ) | const [virtual] |
reMaterialize - Re-issue the specified 'original' instruction at the specific location targeting a new destination register.
Reimplemented from llvm::TargetInstrInfoImpl.
Definition at line 893 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getSubReg(), llvm::MachineBasicBlock::insert(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), isSafeToClobberEFLAGS(), MI, llvm::prior(), llvm::MachineOperand::setReg(), and llvm::MachineOperand::setSubReg().
| bool X86InstrInfo::isInvariantLoad | ( | const MachineInstr * | MI | ) | const [virtual] |
isInvariantLoad - Return true if the specified instruction (which is marked mayLoad) is loading from a location whose value is invariant across the function. For example, loading a value from the constant pool or from from the argument area of a function if it does not change. This should only return true of *all* loads the instruction does are invariant (if it does multiple loads).
Reimplemented from llvm::TargetInstrInfo.
Definition at line 948 of file X86InstrInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), Idx, llvm::MachineOperand::isCPI(), llvm::MachineOperand::isFI(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::MachineOperand::isGlobal(), isGVStub(), llvm::MachineFrameInfo::isImmutableObjectIndex(), and MFI.
| MachineInstr * X86InstrInfo::convertToThreeAddress | ( | MachineFunction::iterator & | MFI, | |
| MachineBasicBlock::iterator & | MBBI, | |||
| LiveVariables * | LV | |||
| ) | const [virtual] |
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1003 of file X86InstrInfo.cpp.
References A, llvm::addFullAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::addRegOffset(), llvm::addRegReg(), llvm::BuildMI(), llvm::CallingConv::C, llvm::MachineRegisterInfo::createVirtualRegister(), Dest, llvm::ISD::EXTRACT_SUBREG, llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::TargetMachine::getSubtarget(), llvm::LiveVariables::getVarInfo(), hasLiveCondCodeDef(), llvm::X86AddressMode::IndexReg, llvm::ISD::INSERT_SUBREG, llvm::MachineOperand::isDead(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), M, MF, MI, RegInfo, llvm::LiveVariables::replaceKillInstruction(), llvm::X86AddressMode::Scale, Src, and llvm::X86::SUBREG_16BIT.
| MachineInstr * X86InstrInfo::commuteInstruction | ( | MachineInstr * | MI, | |
| bool | NewMI | |||
| ) | const [virtual] |
commuteInstruction - We have a few instructions that must be hacked on to commute them.
commuteInstruction - We have a few instructions that must be hacked on to commute them.
Reimplemented from llvm::TargetInstrInfoImpl.
Definition at line 1247 of file X86InstrInfo.cpp.
References llvm::MachineFunction::CloneMachineInstr(), llvm::TargetInstrInfoImpl::commuteInstruction(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), MF, llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setImm().
| bool X86InstrInfo::isUnpredicatedTerminator | ( | const MachineInstr * | MI | ) | const [virtual] |
isUnpredicatedTerminator - Returns true if the instruction is a terminator instruction that has not been predicated.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1457 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::TargetInstrDesc::isBarrier(), llvm::TargetInstrDesc::isBranch(), llvm::TargetInstrDesc::isPredicable(), llvm::TargetInstrInfo::isPredicated(), and llvm::TargetInstrDesc::isTerminator().
Referenced by isBrAnalysisUnpredicatedTerminator().
| bool X86InstrInfo::AnalyzeBranch | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock *& | TBB, | |||
| MachineBasicBlock *& | FBB, | |||
| SmallVectorImpl< MachineOperand > & | Cond | |||
| ) | const [virtual] |
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with an conditional branch and it falls through to an successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with an conditional branch and an unconditional block, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that RemoveBranch and InsertBranch must be implemented to support cases where this method returns success.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1477 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::SmallVectorImpl< T >::clear(), llvm::X86::COND_E, llvm::X86::COND_INVALID, llvm::X86::COND_NE, llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP, llvm::X86::COND_NP_OR_E, llvm::X86::COND_P, llvm::MachineOperand::CreateImm(), llvm::SmallVectorImpl< T >::empty(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::eraseFromParent(), GetCondFromBranchOpc(), I, isBrAnalysisUnpredicatedTerminator(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::next(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().
| unsigned X86InstrInfo::RemoveBranch | ( | MachineBasicBlock & | MBB | ) | const [virtual] |
RemoveBranch - Remove the branching code at the end of the specific MBB. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1560 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::X86::COND_INVALID, llvm::MachineBasicBlock::end(), GetCondFromBranchOpc(), and I.
| unsigned X86InstrInfo::InsertBranch | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock * | TBB, | |||
| MachineBasicBlock * | FBB, | |||
| const SmallVectorImpl< MachineOperand > & | Cond | |||
| ) | const [virtual] |
InsertBranch - Insert a branch into the end of the specified MachineBasicBlock. This operands to this method are the same as those returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch returns success and when an unconditional branch (TBB is non-null, FBB is null, Cond is empty) needs to be inserted. It returns the number of instructions inserted.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1602 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::BuildMI(), llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP_OR_E, llvm::SmallVectorImpl< T >::empty(), GetCondBranchFromCond(), and llvm::SmallVectorImpl< T >::size().
| bool X86InstrInfo::copyRegToReg | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | DestReg, | |||
| unsigned | SrcReg, | |||
| const TargetRegisterClass * | DestRC, | |||
| const TargetRegisterClass * | SrcRC | |||
| ) | const [virtual] |
copyRegToReg - Emit instructions to copy between a pair of registers. It returns false if the target does not how to copy between the specified registers.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1649 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), and llvm::BuildMI().
| void X86InstrInfo::storeRegToStackSlot | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | SrcReg, | |||
| bool | isKill, | |||
| int | FrameIndex, | |||
| const TargetRegisterClass * | RC | |||
| ) | const [virtual] |
storeRegToStackSlot - Store the specified register of the given register class to the specified stack frame index. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1799 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::getParent(), llvm::X86RegisterInfo::getStackAlignment(), getStoreRegOpcode(), MF, and llvm::X86RegisterInfo::needsStackRealignment().
| void X86InstrInfo::storeRegToAddr | ( | MachineFunction & | MF, | |
| unsigned | SrcReg, | |||
| bool | isKill, | |||
| SmallVectorImpl< MachineOperand > & | Addr, | |||
| const TargetRegisterClass * | RC, | |||
| SmallVectorImpl< MachineInstr * > & | NewMIs | |||
| ) | const [virtual] |
storeRegToAddr - Store the specified register of the given register class to the specified address. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1811 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::X86RegisterInfo::getStackAlignment(), getStoreRegOpcode(), llvm::X86RegisterInfo::needsStackRealignment(), llvm::SmallVectorImpl< T >::push_back(), llvm::SmallVectorImpl< T >::size(), and X86InstrAddOperand().
Referenced by unfoldMemoryOperand().
| void X86InstrInfo::loadRegFromStackSlot | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | DestReg, | |||
| int | FrameIndex, | |||
| const TargetRegisterClass * | RC | |||
| ) | const [virtual] |
loadRegFromStackSlot - Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine basic block before the specified machine instruction.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1864 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::BuildMI(), getLoadRegOpcode(), llvm::MachineBasicBlock::getParent(), llvm::X86RegisterInfo::getStackAlignment(), MF, and llvm::X86RegisterInfo::needsStackRealignment().
| void X86InstrInfo::loadRegFromAddr | ( | MachineFunction & | MF, | |
| unsigned | DestReg, | |||
| SmallVectorImpl< MachineOperand > & | Addr, | |||
| const TargetRegisterClass * | RC, | |||
| SmallVectorImpl< MachineInstr * > & | NewMIs | |||
| ) | const [virtual] |
loadRegFromAddr - Load the specified register of the given register class class from the specified address. The load instruction is to be added to the given machine basic block before the specified machine instruction.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1875 of file X86InstrInfo.cpp.
References llvm::BuildMI(), getLoadRegOpcode(), llvm::X86RegisterInfo::getStackAlignment(), llvm::X86RegisterInfo::needsStackRealignment(), llvm::SmallVectorImpl< T >::push_back(), llvm::SmallVectorImpl< T >::size(), and X86InstrAddOperand().
Referenced by unfoldMemoryOperand().
| bool X86InstrInfo::spillCalleeSavedRegisters | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| const std::vector< CalleeSavedInfo > & | CSI | |||
| ) | const [virtual] |
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot(). Returns false otherwise.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1888 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::TargetMachine::getSubtarget(), MF, Reg, and llvm::X86MachineFunctionInfo::setCalleeSavedFrameSize().
| bool X86InstrInfo::restoreCalleeSavedRegisters | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| const std::vector< CalleeSavedInfo > & | CSI | |||
| ) | const [virtual] |
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot(). Returns false otherwise.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 1912 of file X86InstrInfo.cpp.
References llvm::BuildMI(), llvm::TargetMachine::getSubtarget(), and Reg.
| MachineInstr * X86InstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, | |
| MachineInstr * | MI, | |||
| const SmallVectorImpl< unsigned > & | Ops, | |||
| int | FrameIndex | |||
| ) | const [virtual] |
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2050 of file X86InstrInfo.cpp.
References Alignment, llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateFI(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), MFI, NoFusing, llvm::SmallVectorImpl< T >::push_back(), llvm::MachineInstr::setDesc(), and llvm::SmallVectorImpl< T >::size().
Referenced by foldMemoryOperandImpl().
| MachineInstr * X86InstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, | |
| MachineInstr * | MI, | |||
| const SmallVectorImpl< unsigned > & | Ops, | |||
| MachineInstr * | LoadMI | |||
| ) | const [virtual] |
foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2097 of file X86InstrInfo.cpp.
References Alignment, llvm::CallingConv::C, llvm::MachineOperand::ChangeToImmediate(), CPI, llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), foldMemoryOperandImpl(), llvm::VectorType::get(), llvm::ConstantVector::getAllOnesValue(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::MachineInstr::getDesc(), llvm::Constant::getNullValue(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetMachine::getRelocationModel(), llvm::TargetMachine::getSubtarget(), llvm::MachineInstr::hasOneMemOperand(), llvm::Type::Int32Ty, MCP, llvm::MachineInstr::memoperands_begin(), NoFusing, llvm::Reloc::PIC_, llvm::SmallVectorImpl< T >::push_back(), llvm::MachineInstr::setDesc(), llvm::SmallVectorImpl< T >::size(), and Ty.
| bool X86InstrInfo::canFoldMemoryOperand | ( | const MachineInstr * | MI, | |
| const SmallVectorImpl< unsigned > & | Ops | |||
| ) | const [virtual] |
canFoldMemoryOperand - Returns true if the specified load / store is folding is possible.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2181 of file X86InstrInfo.cpp.
References llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::end(), llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::find(), llvm::MachineInstr::getDesc(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::TargetInstrDesc::getOperandConstraint(), NoFusing, llvm::SmallVectorImpl< T >::size(), and llvm::TOI::TIED_TO.
| bool X86InstrInfo::unfoldMemoryOperand | ( | MachineFunction & | MF, | |
| MachineInstr * | MI, | |||
| unsigned | Reg, | |||
| bool | UnfoldLoad, | |||
| bool | UnfoldStore, | |||
| SmallVectorImpl< MachineInstr * > & | NewMIs | |||
| ) | const [virtual] |
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. If this is possible, returns true as well as the new instructions by reference.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2238 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineFunction::CreateMachineInstr(), llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::end(), llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::find(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getPointerRegClass(), llvm::MachineOperand::getReg(), Index, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isKill(), llvm::TargetOperandInfo::isLookupPtrRegClass(), llvm::MachineOperand::isReg(), loadRegFromAddr(), Op, llvm::TargetInstrDesc::OpInfo, llvm::SmallVectorImpl< T >::push_back(), llvm::TargetOperandInfo::RegClass, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::SmallVectorImpl< T >::size(), storeRegToAddr(), and X86InstrAddOperand().
| bool X86InstrInfo::unfoldMemoryOperand | ( | SelectionDAG & | DAG, | |
| SDNode * | N, | |||
| SmallVectorImpl< SDNode * > & | NewNodes | |||
| ) | const [virtual] |
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2342 of file X86InstrInfo.cpp.
References llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::end(), llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::find(), getLoadRegOpcode(), llvm::SelectionDAG::getMachineFunction(), llvm::SDNode::getMachineOpcode(), llvm::TargetInstrDesc::getNumDefs(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOperand(), getPointerRegClass(), llvm::X86RegisterInfo::getStackAlignment(), getStoreRegOpcode(), llvm::SelectionDAG::getTargetNode(), llvm::SDNode::getValueType(), Index, llvm::TargetOperandInfo::isLookupPtrRegClass(), llvm::SDNode::isMachineOpcode(), llvm::Load, llvm::X86RegisterInfo::needsStackRealignment(), Op, llvm::TargetInstrDesc::OpInfo, llvm::MVT::Other, llvm::SmallVectorImpl< T >::push_back(), llvm::TargetOperandInfo::RegClass, llvm::SPII::Store, VT, and llvm::TargetRegisterClass::vt_begin().
| unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold | ( | unsigned | Opc, | |
| bool | UnfoldLoad, | |||
| bool | UnfoldStore | |||
| ) | const [virtual] |
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. It returns zero if the specified unfolding is not possible.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2423 of file X86InstrInfo.cpp.
References llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::end(), and llvm::DenseMap< KeyT, ValueT, KeyInfoT, ValueInfoT >::find().
| bool X86InstrInfo::BlockHasNoFallThrough | ( | const MachineBasicBlock & | MBB | ) | const [virtual] |
BlockHasNoFallThrough - Return true if the specified block does not fall-through into its successor block. This is primarily used when a branch is unanalyzable. It is useful for things like unconditional indirect branches (jump tables).
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2438 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::empty(), llvm::MachineInstr::getOpcode(), and llvm::ISD::RET.
| bool X86InstrInfo::ReverseBranchCondition | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const [virtual] |
ReverseBranchCondition - Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2460 of file X86InstrInfo.cpp.
References llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP_OR_E, GetOppositeBranchCondition(), and llvm::SmallVectorImpl< T >::size().
| bool X86InstrInfo::IgnoreRegisterClassBarriers | ( | const TargetRegisterClass * | RC | ) | const [virtual] |
IgnoreRegisterClassBarriers - Returns true if pre-register allocation live interval splitting pass should ignore barriers of the specified register class.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2470 of file X86InstrInfo.cpp.
| const TargetRegisterClass * X86InstrInfo::getPointerRegClass | ( | ) | const [virtual] |
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
Reimplemented from llvm::TargetInstrInfo.
Definition at line 2477 of file X86InstrInfo.cpp.
References llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::is64Bit(), and Subtarget.
Referenced by unfoldMemoryOperand().
| unsigned char llvm::X86InstrInfo::getBaseOpcodeFor | ( | const TargetInstrDesc * | TID | ) | const [inline] |
Definition at line 418 of file X86InstrInfo.h.
References llvm::X86II::OpcodeShift, and llvm::TargetInstrDesc::TSFlags.
Referenced by getBaseOpcodeFor().
| static bool llvm::X86InstrInfo::isX86_64NonExtLowByteReg | ( | unsigned | reg | ) | [inline, static] |
| unsigned X86InstrInfo::sizeOfImm | ( | const TargetInstrDesc * | Desc | ) | [static] |
Definition at line 2485 of file X86InstrInfo.cpp.
References llvm::X86II::Imm16, llvm::X86II::Imm32, llvm::X86II::Imm64, llvm::X86II::Imm8, llvm::X86II::ImmMask, and llvm::TargetInstrDesc::TSFlags.
Referenced by GetInstSizeWithDesc().
| bool X86InstrInfo::isX86_64ExtendedReg | ( | const MachineOperand & | MO | ) | [static] |
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register? e.g. r8, xmm8, etc.
Definition at line 2498 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().
Referenced by determineREX().
| unsigned X86InstrInfo::determineREX | ( | const MachineInstr & | MI | ) | [static] |
determineREX - Determine if the MachineInstr has to be encoded with a X86-64 REX prefix which specifies 1) 64-bit instructions, 2) non-default operand size, and 3) use of X86-64 extended registers.
Definition at line 2521 of file X86InstrInfo.cpp.
References llvm::X86II::FormMask, llvm::MachineInstr::getDesc(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::TargetInstrDesc::getOperandConstraint(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), isX86_64ExtendedReg(), isX86_64NonExtLowByteReg(), llvm::X86II::MRM0m, llvm::X86II::MRM1m, llvm::X86II::MRM2m,