LLVM API Documentation

llvm::TargetLowering Class Reference

#include <TargetLowering.h>

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List of all members.

Public Types

enum  LegalizeAction { Legal, Promote, Expand, Custom }
enum  OutOfRangeShiftAmount { Undefined, Mask, Extend }
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
enum  SchedPreference { SchedulingForLatency, SchedulingForRegPressure }
enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}
typedef struct
llvm::TargetLowering::IntrinsicInfo 
IntrinisicInfo
typedef std::vector< APFloat >
::const_iterator 
legal_fpimm_iterator
typedef std::vector< ArgListEntryArgListTy

Public Member Functions

 TargetLowering (TargetMachine &TM)
virtual ~TargetLowering ()
TargetMachinegetTargetMachine () const
const TargetDatagetTargetData () const
bool isBigEndian () const
bool isLittleEndian () const
MVT getPointerTy () const
MVT getShiftAmountTy () const
OutOfRangeShiftAmount getShiftAmountFlavor () const
bool usesGlobalOffsetTable () const
bool isSelectExpensive () const
bool isIntDivCheap () const
bool isPow2DivCheap () const
virtual MVT getSetCCResultType (MVT VT) const
BooleanContent getBooleanContents () const
SchedPreference getSchedulingPreference () const
 getSchedulingPreference - Return target scheduling preference.
TargetRegisterClassgetRegClassFor (MVT VT) const
bool isTypeLegal (MVT VT) const
const ValueTypeActionImplgetValueTypeActions () const
LegalizeAction getTypeAction (MVT VT) const
MVT getTypeToTransformTo (MVT VT) const
MVT getTypeToExpandTo (MVT VT) const
unsigned getVectorTypeBreakdown (MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
virtual bool getTgtMemIntrinsic (IntrinsicInfo &Info, CallInst &I, unsigned Intrinsic)
virtual MVT getWidenVectorType (MVT VT)
legal_fpimm_iterator legal_fpimm_begin () const
legal_fpimm_iterator legal_fpimm_end () const
virtual bool isShuffleMaskLegal (SDValue Mask, MVT VT) const
virtual bool isVectorClearMaskLegal (const std::vector< SDValue > &BVOps, MVT EVT, SelectionDAG &DAG) const
LegalizeAction getOperationAction (unsigned Op, MVT VT) const
bool isOperationLegal (unsigned Op, MVT VT) const
LegalizeAction getLoadExtAction (unsigned LType, MVT VT) const
bool isLoadExtLegal (unsigned LType, MVT VT) const
LegalizeAction getTruncStoreAction (MVT ValVT, MVT MemVT) const
bool isTruncStoreLegal (MVT ValVT, MVT MemVT) const
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
bool isIndexedLoadLegal (unsigned IdxMode, MVT VT) const
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
bool isIndexedStoreLegal (unsigned IdxMode, MVT VT) const
LegalizeAction getConvertAction (MVT FromVT, MVT ToVT) const
bool isConvertLegal (MVT FromVT, MVT ToVT) const
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
MVT getValueType (const Type *Ty, bool AllowUnknown=false) const
virtual unsigned getByValTypeAlignment (const Type *Ty) const
MVT getRegisterType (MVT VT) const
unsigned getNumRegisters (MVT VT) const
virtual bool ShouldShrinkFPConstant (MVT VT) const
bool hasTargetDAGCombine (ISD::NodeType NT) const
unsigned getMaxStoresPerMemset () const
 Get maximum # of store operations permitted for llvm.memset.
unsigned getMaxStoresPerMemcpy () const
 Get maximum # of store operations permitted for llvm.memcpy.
unsigned getMaxStoresPerMemmove () const
 Get maximum # of store operations permitted for llvm.memmove.
bool allowsUnalignedMemoryAccesses () const
 Determine if the target supports unaligned memory accesses.
virtual MVT getOptimalMemOpType (uint64_t Size, unsigned Align, bool isSrcConst, bool isSrcStr) const
bool usesUnderscoreSetJmp () const
bool usesUnderscoreLongJmp () const
unsigned getStackPointerRegisterToSaveRestore () const
unsigned getExceptionAddressRegister () const
unsigned getExceptionSelectorRegister () const
unsigned getJumpBufSize () const
unsigned getJumpBufAlignment () const
unsigned getIfCvtBlockSizeLimit () const
unsigned getIfCvtDupBlockSizeLimit () const
unsigned getPrefLoopAlignment () const
virtual bool getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG)
virtual bool getPostIndexedAddressParts (SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG)
virtual SDValue getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
virtual bool isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
virtual void computeMaskedBitsForTargetNode (const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
virtual unsigned ComputeNumSignBitsForTargetNode (SDValue Op, unsigned Depth=0) const
SDValue SimplifySetCC (MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI) const
virtual bool isGAPlusOffset (SDNode *N, GlobalValue *&GA, int64_t &Offset) const
bool isConsecutiveLoad (SDNode *LD, SDNode *Base, unsigned Bytes, int Dist, const MachineFrameInfo *MFI) const
virtual SDValue PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const
virtual const TargetSubtargetgetSubtarget ()
virtual void LowerArguments (Function &F, SelectionDAG &DAG, SmallVectorImpl< SDValue > &ArgValues)
virtual std::pair< SDValue,
SDValue
LowerCallTo (SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg, unsigned CallingConv, bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG)
virtual SDValue EmitTargetCodeForMemcpy (SelectionDAG &DAG, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstOff, const Value *SrcSV, uint64_t SrcOff)
virtual SDValue EmitTargetCodeForMemmove (SelectionDAG &DAG, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, const Value *DstSV, uint64_t DstOff, const Value *SrcSV, uint64_t SrcOff)
virtual SDValue EmitTargetCodeForMemset (SelectionDAG &DAG, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, const Value *DstSV, uint64_t DstOff)
virtual SDValue LowerOperation (SDValue Op, SelectionDAG &DAG)
virtual void ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
virtual bool IsEligibleForTailCallOptimization (CallSDNode *Call, SDValue Ret, SelectionDAG &DAG) const
virtual const char * getTargetNodeName (unsigned Opcode) const
virtual FastISelcreateFastISel (MachineFunction &, MachineModuleInfo *, DenseMap< const Value *, unsigned > &, DenseMap< const BasicBlock *, MachineBasicBlock * > &, DenseMap< const AllocaInst *, int > &, SmallSet< Instruction *, 8 > &CatchInfoLost)
virtual void ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, bool hasMemory, SelectionDAG *DAG=0) const
virtual ConstraintType getConstraintType (const std::string &Constraint) const
virtual std::vector< unsignedgetRegClassForInlineAsmConstraint (const std::string &Constraint, MVT VT) const
virtual std::pair< unsigned,
const TargetRegisterClass * > 
getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const
virtual const char * LowerXConstraint (MVT ConstraintVT) const
virtual void LowerAsmOperandForConstraint (SDValue Op, char ConstraintLetter, bool hasMemory, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
virtual MachineBasicBlockEmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB)
virtual bool isLegalAddressingMode (const AddrMode &AM, const Type *Ty) const
virtual bool isTruncateFree (const Type *Ty1, const Type *Ty2) const
virtual bool isTruncateFree (MVT VT1, MVT VT2) const
SDValue BuildSDIV (SDNode *N, SelectionDAG &DAG, std::vector< SDNode * > *Created) const
SDValue BuildUDIV (SDNode *N, SelectionDAG &DAG, std::vector< SDNode * > *Created) const
void setLibcallName (RTLIB::Libcall Call, const char *Name)
const char * getLibcallName (RTLIB::Libcall Call) const
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const

Static Public Member Functions

static bool CheckTailCallReturnConstraints (CallSDNode *TheCall, SDValue Ret)
static SDValue GetPossiblePreceedingTailCall (SDValue Chain, unsigned TailCallNodeOpCode)

Protected Member Functions

void setUsesGlobalOffsetTable (bool V)
void setShiftAmountType (MVT VT)
void setBooleanContents (BooleanContent Ty)
void setSchedulingPreference (SchedPreference Pref)
 setSchedulingPreference - Specify the target scheduling preference.
void setShiftAmountFlavor (OutOfRangeShiftAmount OORSA)
void setUseUnderscoreSetJmp (bool Val)
void setUseUnderscoreLongJmp (bool Val)
void setStackPointerRegisterToSaveRestore (unsigned R)
void setExceptionPointerRegister (unsigned R)
void setExceptionSelectorRegister (unsigned R)
void setSelectIsExpensive ()
void setIntDivIsCheap (bool isCheap=true)
void setPow2DivIsCheap (bool isCheap=true)
void addRegisterClass (MVT VT, TargetRegisterClass *RC)
void computeRegisterProperties ()
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
void setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
void setConvertAction (MVT FromVT, MVT ToVT, LegalizeAction Action)
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
void addLegalFPImmediate (const APFloat &Imm)
void setTargetDAGCombine (ISD::NodeType NT)
void setJumpBufSize (unsigned Size)
void setJumpBufAlignment (unsigned Align)
void setIfCvtBlockSizeLimit (unsigned Limit)
void setIfCvtDupBlockSizeLimit (unsigned Limit)
void setPrefLoopAlignment (unsigned Align)

Protected Attributes

unsigned maxStoresPerMemset
 Specify maximum number of store instructions per memset call.
unsigned maxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call.
unsigned maxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call.
bool allowUnalignedMemoryAccesses
 Indicate whether the target permits unaligned memory accesses.

Classes

struct  AddrMode
struct  ArgListEntry
struct  AsmOperandInfo
struct  DAGCombinerInfo
struct  IntrinsicInfo
struct  TargetLoweringOpt
class  ValueTypeActionImpl


Detailed Description

TargetLowering - This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively.

This class also defines callbacks that targets must implement to lower target-specific constructs to SelectionDAG operators.

Definition at line 63 of file TargetLowering.h.


Member Typedef Documentation

getTgtMemIntrinsic: Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

typedef std::vector<APFloat>::const_iterator llvm::TargetLowering::legal_fpimm_iterator

Definition at line 304 of file TargetLowering.h.

Definition at line 1071 of file TargetLowering.h.


Member Enumeration Documentation

LegalizeAction - This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator:
Legal 
Promote 
Expand 
Custom 

Definition at line 67 of file TargetLowering.h.

Enumerator:
Undefined 
Mask 
Extend 

Definition at line 74 of file TargetLowering.h.

Enumerator:
UndefinedBooleanContent 
ZeroOrOneBooleanContent 
ZeroOrNegativeOneBooleanContent 

Definition at line 80 of file TargetLowering.h.

Enumerator:
SchedulingForLatency 
SchedulingForRegPressure 

Definition at line 86 of file TargetLowering.h.

Enumerator:
C_Register 
C_RegisterClass 
C_Memory 
C_Other 
C_Unknown 

Definition at line 1217 of file TargetLowering.h.


Constructor & Destructor Documentation

TargetLowering::TargetLowering ( TargetMachine TM  )  [explicit]

TargetLowering::~TargetLowering (  )  [virtual]

Definition at line 480 of file TargetLowering.cpp.


Member Function Documentation

TargetMachine& llvm::TargetLowering::getTargetMachine (  )  const [inline]

const TargetData* llvm::TargetLowering::getTargetData (  )  const [inline]

bool llvm::TargetLowering::isBigEndian (  )  const [inline]

Definition at line 97 of file TargetLowering.h.

Referenced by getCopyFromParts(), and getCopyToParts().

bool llvm::TargetLowering::isLittleEndian (  )  const [inline]

Definition at line 98 of file TargetLowering.h.

Referenced by ExpandUnalignedLoad(), ExpandUnalignedStore(), and getMemsetStringVal().

MVT llvm::TargetLowering::getPointerTy (  )  const [inline]

MVT llvm::TargetLowering::getShiftAmountTy (  )  const [inline]

OutOfRangeShiftAmount llvm::TargetLowering::getShiftAmountFlavor (  )  const [inline]

Definition at line 101 of file TargetLowering.h.

bool llvm::TargetLowering::usesGlobalOffsetTable (  )  const [inline]

usesGlobalOffsetTable - Return true if this target uses a GOT for PIC codegen.

Definition at line 105 of file TargetLowering.h.

Referenced by llvm::AsmPrinter::EmitJumpTableInfo(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), and getPICJumpTableRelocBase().

bool llvm::TargetLowering::isSelectExpensive (  )  const [inline]

isSelectExpensive - Return true if the select operation is expensive for this target.

Definition at line 109 of file TargetLowering.h.

bool llvm::TargetLowering::isIntDivCheap (  )  const [inline]

isIntDivCheap() - Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

Definition at line 113 of file TargetLowering.h.

bool llvm::TargetLowering::isPow2DivCheap (  )  const [inline]

isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of srl/add/sra.

Definition at line 117 of file TargetLowering.h.

MVT TargetLowering::getSetCCResultType ( MVT  VT  )  const [virtual]

getSetCCResultType - Return the ValueType of the result of SETCC operations. Also used to obtain the target's preferred type for the condition operand of SELECT and BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other since there are no other operands to get a type hint from.

Reimplemented in llvm::AlphaTargetLowering, llvm::SPUTargetLowering, llvm::IA64TargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 608 of file TargetLowering.cpp.

References llvm::TargetData::getIntPtrType(), and getValueType().

Referenced by LowerSELECT_CC(), llvm::SelectionDAGLowering::visitBitTestCase(), llvm::SelectionDAGLowering::visitBitTestHeader(), and llvm::SelectionDAGLowering::visitJumpTableHeader().

BooleanContent llvm::TargetLowering::getBooleanContents (  )  const [inline]

getBooleanContents - For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. "Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1.

Definition at line 131 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::ComputeMaskedBits(), and llvm::SelectionDAG::ComputeNumSignBits().

SchedPreference llvm::TargetLowering::getSchedulingPreference (  )  const [inline]

getSchedulingPreference - Return target scheduling preference.

Definition at line 134 of file TargetLowering.h.

Referenced by llvm::createDefaultScheduler().

TargetRegisterClass* llvm::TargetLowering::getRegClassFor ( MVT  VT  )  const [inline]

getRegClassFor - Return the register class that should be used for the specified value type. This may only be called on legal types.

Definition at line 140 of file TargetLowering.h.

References llvm::array_lengthof(), and llvm::MVT::getSimpleVT().

Referenced by CheckDAGForTailCallsAndFixThem(), llvm::FastISel::getRegForValue(), llvm::IA64TargetLowering::LowerArguments(), llvm::SelectionDAGISel::MakeReg(), and llvm::FunctionLoweringInfo::MakeReg().

bool llvm::TargetLowering::isTypeLegal ( MVT  VT  )  const [inline]

const ValueTypeActionImpl& llvm::TargetLowering::getValueTypeActions (  )  const [inline]

Definition at line 192 of file TargetLowering.h.

LegalizeAction llvm::TargetLowering::getTypeAction ( MVT  VT  )  const [inline]

getTypeAction - Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Definition at line 200 of file TargetLowering.h.

References llvm::TargetLowering::ValueTypeActionImpl::getTypeAction().

Referenced by getTypeToExpandTo(), getTypeToTransformTo(), and OptimizeNoopCopyExpression().

MVT llvm::TargetLowering::getTypeToTransformTo ( MVT  VT  )  const [inline]

getTypeToTransformTo - For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 210 of file TargetLowering.h.

References llvm::array_lengthof(), llvm::MVT::getIntegerVT(), llvm::MVT::getPow2VectorType(), llvm::MVT::getRoundIntegerType(), llvm::MVT::getSimpleVT(), llvm::MVT::getSizeInBits(), getTypeAction(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::isInteger(), llvm::MVT::isSimple(), llvm::MVT::isVector(), and Promote.

Referenced by llvm::FastISel::getRegForValue(), getRegisterType(), getTypeToExpandTo(), getVectorTypeBreakdown(), and OptimizeNoopCopyExpression().