llvm::TargetInstrInfo Class Reference
#include <TargetInstrInfo.h>
Detailed Description
TargetInstrInfo - Interface to description of machine instruction setDefinition at line 35 of file TargetInstrInfo.h.
Member Enumeration Documentation
| anonymous enum |
- Enumerator:
-
PHI INLINEASM DBG_LABEL EH_LABEL GC_LABEL DECLARE EXTRACT_SUBREG INSERT_SUBREG IMPLICIT_DEF SUBREG_TO_REG
Definition at line 46 of file TargetInstrInfo.h.
Constructor & Destructor Documentation
| TargetInstrInfo::TargetInstrInfo | ( | const TargetInstrDesc * | desc, | |
| unsigned | NumOpcodes | |||
| ) |
Definition at line 32 of file TargetInstrInfo.cpp.
| TargetInstrInfo::~TargetInstrInfo | ( | ) | [virtual] |
Definition at line 37 of file TargetInstrInfo.cpp.
Member Function Documentation
| unsigned llvm::TargetInstrInfo::getNumOpcodes | ( | ) | const [inline] |
| const TargetInstrDesc& llvm::TargetInstrInfo::get | ( | unsigned | Opcode | ) | const [inline] |
get - Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition at line 64 of file TargetInstrInfo.h.
Referenced by canClobberPhysRegDefs(), CheckForPhysRegDependency(), llvm::ScheduleDAGSDNodes::ComputeLatency(), llvm::XCoreRegisterInfo::eliminateCallFramePseudoInstr(), llvm::X86RegisterInfo::eliminateCallFramePseudoInstr(), llvm::SparcRegisterInfo::eliminateCallFramePseudoInstr(), llvm::PPCRegisterInfo::eliminateCallFramePseudoInstr(), llvm::IA64RegisterInfo::eliminateCallFramePseudoInstr(), llvm::AlphaRegisterInfo::eliminateCallFramePseudoInstr(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::IA64RegisterInfo::eliminateFrameIndex(), llvm::ARMRegisterInfo::eliminateFrameIndex(), llvm::AlphaRegisterInfo::eliminateFrameIndex(), emitARMRegPlusImmediate(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::XCoreRegisterInfo::emitEpilogue(), llvm::X86RegisterInfo::emitEpilogue(), llvm::SPURegisterInfo::emitEpilogue(), llvm::SparcRegisterInfo::emitEpilogue(), llvm::PPCRegisterInfo::emitEpilogue(), llvm::MipsRegisterInfo::emitEpilogue(), llvm::IA64RegisterInfo::emitEpilogue(), llvm::ARMRegisterInfo::emitEpilogue(), llvm::AlphaRegisterInfo::emitEpilogue(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::SparcTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::AlphaTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMRegisterInfo::emitLoadConstPool(), llvm::ScheduleDAGSDNodes::EmitNode(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::XCoreRegisterInfo::emitPrologue(), llvm::X86RegisterInfo::emitPrologue(), llvm::SPURegisterInfo::emitPrologue(), llvm::SparcRegisterInfo::emitPrologue(), llvm::PPCRegisterInfo::emitPrologue(), llvm::MipsRegisterInfo::emitPrologue(), llvm::IA64RegisterInfo::emitPrologue(), llvm::ARMRegisterInfo::emitPrologue(), llvm::AlphaRegisterInfo::emitPrologue(), emitSPUpdate(), emitThumbConstant(), emitThumbRegPlusImmediate(), emitThumbRegPlusImmInReg(), llvm::FastISel::FastEmitInst_(), llvm::FastISel::FastEmitInst_extractsubreg(), llvm::FastISel::FastEmitInst_i(), llvm::FastISel::FastEmitInst_r(), llvm::FastISel::FastEmitInst_rf(), llvm::FastISel::FastEmitInst_ri(), llvm::FastISel::FastEmitInst_rr(), llvm::FastISel::FastEmitInst_rri(), FuseInst(), FuseTwoAddrInst(), llvm::X86InstrInfo::getGlobalBaseReg(), llvm::SDNode::getOperationName(), getPhysicalRegisterVT(), llvm::FastISel::getRegForValue(), HandleVRSaveUpdate(), llvm::IA64TargetLowering::LowerArguments(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), MakeM0Inst(), mergeBaseUpdateLoadStore(), mergeOps(), llvm::ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(), and llvm::FunctionLoweringInfo::set().
| bool llvm::TargetInstrInfo::isTriviallyReMaterializable | ( | const MachineInstr * | MI | ) | const [inline] |
isTriviallyReMaterializable - Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available.
Definition at line 72 of file TargetInstrInfo.h.
References llvm::MachineInstr::getDesc(), isReallyTriviallyReMaterializable(), and llvm::TargetInstrDesc::isRematerializable().
Referenced by llvm::MachineInstr::isSafeToReMat().
| virtual bool llvm::TargetInstrInfo::isReallyTriviallyReMaterializable | ( | const MachineInstr * | MI | ) | const [inline, protected, virtual] |
isReallyTriviallyReMaterializable - For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this function tests whether the instruction itself is actually trivially rematerializable, considering its operands. This is used for targets that have instructions that are only trivially rematerializable for specific uses. This predicate must return false if the instruction has any side effects other than producing a value, or if it requres any address registers that are not always available.
Reimplemented in llvm::X86InstrInfo.
Definition at line 86 of file TargetInstrInfo.h.
Referenced by isTriviallyReMaterializable().
| virtual bool llvm::TargetInstrInfo::isMoveInstr | ( | const MachineInstr & | MI, | |
| unsigned & | sourceReg, | |||
| unsigned & | destReg | |||
| ) | const [inline, virtual] |
Return true if the instruction is a register to register move and leave the source and dest operands in the passed parameters.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::IA64InstrInfo, llvm::MipsInstrInfo, llvm::PIC16InstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 93 of file TargetInstrInfo.h.
Referenced by llvm::LiveIntervals::conflictsWithPhysRegDef(), EmitLiveInCopy(), llvm::LiveIntervals::getVNInfoSourceReg(), and llvm::SimpleRegisterCoalescing::runOnMachineFunction().
| virtual unsigned llvm::TargetInstrInfo::isLoadFromStackSlot | ( | const MachineInstr * | MI, | |
| int & | FrameIndex | |||
| ) | const [inline, virtual] |
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::MipsInstrInfo, llvm::PIC16InstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 104 of file TargetInstrInfo.h.
Referenced by llvm::LiveIntervals::addIntervalsForSpills().
| virtual unsigned llvm::TargetInstrInfo::isStoreToStackSlot | ( | const MachineInstr * | MI, | |
| int & | FrameIndex | |||
| ) | const [inline, virtual] |
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::MipsInstrInfo, llvm::PIC16InstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 114 of file TargetInstrInfo.h.
| virtual void llvm::TargetInstrInfo::reMaterialize | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | DestReg, | |||
| const MachineInstr * | Orig | |||
| ) | const [pure virtual] |
reMaterialize - Re-issue the specified 'original' instruction at the specific location targeting a new destination register.
Implemented in llvm::TargetInstrInfoImpl, llvm::ARMInstrInfo, and llvm::X86InstrInfo.
Referenced by ReMaterialize().
| virtual bool llvm::TargetInstrInfo::isInvariantLoad | ( | const MachineInstr * | MI | ) | const [inline, virtual] |
isInvariantLoad - Return true if the specified instruction (which is marked mayLoad) is loading from a location whose value is invariant across the function. For example, loading a value from the constant pool or from from the argument area of a function if it does not change. This should only return true of *all* loads the instruction does are invariant (if it does multiple loads).
Reimplemented in llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 132 of file TargetInstrInfo.h.
Referenced by llvm::ScheduleDAGInstrs::BuildSchedGraph(), and llvm::MachineInstr::isSafeToMove().
| virtual MachineInstr* llvm::TargetInstrInfo::convertToThreeAddress | ( | MachineFunction::iterator & | MFI, | |
| MachineBasicBlock::iterator & | MBBI, | |||
| LiveVariables * | LV | |||
| ) | const [inline, virtual] |
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into one or more true three-address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the last new instruction.
Reimplemented in llvm::ARMInstrInfo, and llvm::X86InstrInfo.
Definition at line 147 of file TargetInstrInfo.h.
| virtual MachineInstr* llvm::TargetInstrInfo::commuteInstruction | ( | MachineInstr * | MI, | |
| bool | NewMI = false | |||
| ) | const [pure virtual] |
commuteInstruction - If a target has any instructions that are commutable, but require converting to a different instruction or making non-trivial changes to commute them, this method can overloaded to do this. The default implementation of this method simply swaps the first two operands of MI and returns it.
If a target wants to make more aggressive changes, they can construct and return a new machine instruction. If an instruction cannot commute, it can also return null.
If NewMI is true, then a new machine instruction must be created.
Implemented in llvm::TargetInstrInfoImpl, llvm::PPCInstrInfo, and llvm::X86InstrInfo.
| virtual bool llvm::TargetInstrInfo::CommuteChangesDestination | ( | MachineInstr * | MI, | |
| unsigned & | OpIdx | |||
| ) | const [pure virtual] |
CommuteChangesDestination - Return true if commuting the specified instruction will also changes the destination operand. Also return the current operand index of the would be new destination register by reference. This can happen when the commutable instruction is also a two-address instruction.
Implemented in llvm::TargetInstrInfoImpl.
| virtual bool llvm::TargetInstrInfo::AnalyzeBranch | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock *& | TBB, | |||
| MachineBasicBlock *& | FBB, | |||
| SmallVectorImpl< MachineOperand > & | Cond | |||
| ) | const [inline, virtual] |
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with an conditional branch and it falls through to an successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with an conditional branch and an unconditional block, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that RemoveBranch and InsertBranch must be implemented to support cases where this method returns success.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::MipsInstrInfo, llvm::PPCInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 198 of file TargetInstrInfo.h.
Referenced by FixTail(), and isSameOrFallThroughBB().
| virtual unsigned llvm::TargetInstrInfo::RemoveBranch | ( | MachineBasicBlock & | MBB | ) | const [inline, virtual] |
RemoveBranch - Remove the branching code at the end of the specific MBB. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::MipsInstrInfo, llvm::PPCInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 207 of file TargetInstrInfo.h.
Referenced by FixTail().
| virtual unsigned llvm::TargetInstrInfo::InsertBranch | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock * | TBB, | |||
| MachineBasicBlock * | FBB, | |||
| const SmallVectorImpl< MachineOperand > & | Cond | |||
| ) | const [inline, virtual] |
InsertBranch - Insert a branch into the end of the specified MachineBasicBlock. This operands to this method are the same as those returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch returns success and when an unconditional branch (TBB is non-null, FBB is null, Cond is empty) needs to be inserted. It returns the number of instructions inserted.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::IA64InstrInfo, llvm::MipsInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 218 of file TargetInstrInfo.h.
Referenced by llvm::FastISel::FastEmitBranch(), FixTail(), InsertUncondBranch(), and llvm::SplitCriticalMachineEdge().
| virtual bool llvm::TargetInstrInfo::copyRegToReg | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | DestReg, | |||
| unsigned | SrcReg, | |||
| const TargetRegisterClass * | DestRC, | |||
| const TargetRegisterClass * | SrcRC | |||
| ) | const [inline, virtual] |
copyRegToReg - Emit instructions to copy between a pair of registers. It returns false if the target does not how to copy between the specified registers.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::IA64InstrInfo, llvm::MipsInstrInfo, llvm::PIC16InstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 228 of file TargetInstrInfo.h.
Referenced by llvm::ScheduleDAG::EmitCrossRCCopy(), EmitLiveInCopies(), EmitLiveInCopy(), llvm::ScheduleDAGSDNodes::EmitNode(), llvm::FastISel::FastEmitInst_extractsubreg(), llvm::FastISel::FastEmitInst_i(), llvm::FastISel::FastEmitInst_r(), llvm::FastISel::FastEmitInst_rf(), llvm::FastISel::FastEmitInst_ri(), llvm::FastISel::FastEmitInst_rr(), llvm::FastISel::FastEmitInst_rri(), and llvm::FastISel::UpdateValueMap().
| virtual void llvm::TargetInstrInfo::storeRegToStackSlot | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | SrcReg, | |||
| bool | isKill, | |||
| int | FrameIndex, | |||
| const TargetRegisterClass * | RC | |||
| ) | const [inline, virtual] |
storeRegToStackSlot - Store the specified register of the given register class to the specified stack frame index. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::IA64InstrInfo, llvm::MipsInstrInfo, llvm::PIC16InstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 242 of file TargetInstrInfo.h.
Referenced by llvm::RegScavenger::scavengeRegister().
| virtual void llvm::TargetInstrInfo::storeRegToAddr | ( | MachineFunction & | MF, | |
| unsigned | SrcReg, | |||
| bool | isKill, | |||
| SmallVectorImpl< MachineOperand > & | Addr, | |||
| const TargetRegisterClass * | RC, | |||
| SmallVectorImpl< MachineInstr * > & | NewMIs | |||
| ) | const [inline, virtual] |
storeRegToAddr - Store the specified register of the given register class to the specified address. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::IA64InstrInfo, llvm::MipsInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 254 of file TargetInstrInfo.h.
| virtual void llvm::TargetInstrInfo::loadRegFromStackSlot | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| unsigned | DestReg, | |||
| int | FrameIndex, | |||
| const TargetRegisterClass * | RC | |||
| ) | const [inline, virtual] |
loadRegFromStackSlot - Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine basic block before the specified machine instruction.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::IA64InstrInfo, llvm::MipsInstrInfo, llvm::PIC16InstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 265 of file TargetInstrInfo.h.
Referenced by llvm::RegScavenger::scavengeRegister().
| virtual void llvm::TargetInstrInfo::loadRegFromAddr | ( | MachineFunction & | MF, | |
| unsigned | DestReg, | |||
| SmallVectorImpl< MachineOperand > & | Addr, | |||
| const TargetRegisterClass * | RC, | |||
| SmallVectorImpl< MachineInstr * > & | NewMIs | |||
| ) | const [inline, virtual] |
loadRegFromAddr - Load the specified register of the given register class class from the specified address. The load instruction is to be added to the given machine basic block before the specified machine instruction.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::IA64InstrInfo, llvm::MipsInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 275 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::spillCalleeSavedRegisters | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| const std::vector< CalleeSavedInfo > & | CSI | |||
| ) | const [inline, virtual] |
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot(). Returns false otherwise.
Reimplemented in llvm::ARMInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 286 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::restoreCalleeSavedRegisters | ( | MachineBasicBlock & | MBB, | |
| MachineBasicBlock::iterator | MI, | |||
| const std::vector< CalleeSavedInfo > & | CSI | |||
| ) | const [inline, virtual] |
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot(). Returns false otherwise.
Reimplemented in llvm::ARMInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 296 of file TargetInstrInfo.h.
| MachineInstr * TargetInstrInfo::foldMemoryOperand | ( | MachineFunction & | MF, | |
| MachineInstr * | MI, | |||
| const SmallVectorImpl< unsigned > & | Ops, | |||
| int | FrameIndex | |||
| ) | const |
foldMemoryOperand - Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The client is responsible for removing the old instruction and adding the new one in the instruction stream.
foldMemoryOperand - Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The client is responsible for removing the old instruction and adding the new one in the instruction stream.
Definition at line 137 of file TargetInstrInfoImpl.cpp.
References llvm::MachineInstr::addMemOperand(), foldMemoryOperandImpl(), llvm::MachineInstr::getDesc(), llvm::PseudoSourceValue::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isDef(), llvm::TargetInstrDesc::mayLoad(), llvm::TargetInstrDesc::mayStore(), MFI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, and llvm::SmallVectorImpl< T >::size().
| MachineInstr * TargetInstrInfo::foldMemoryOperand | ( | MachineFunction & | MF, | |
| MachineInstr * | MI, | |||
| const SmallVectorImpl< unsigned > & | Ops, | |||
| MachineInstr * | LoadMI | |||
| ) | const |
foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 174 of file TargetInstrInfoImpl.cpp.
References llvm::MachineInstr::addMemOperand(), llvm::TargetInstrDesc::canFoldAsLoad(), E, foldMemoryOperandImpl(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), I, llvm::MachineOperand::isUse(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), and llvm::SmallVectorImpl< T >::size().
| virtual MachineInstr* llvm::TargetInstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, | |
| MachineInstr * | MI, | |||
| const SmallVectorImpl< unsigned > & | Ops, | |||
| int | FrameIndex | |||
| ) | const [inline, protected, virtual] |
foldMemoryOperandImpl - Target-dependent implementation for foldMemoryOperand. Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::MipsInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, and llvm::X86InstrInfo.
Definition at line 325 of file TargetInstrInfo.h.
Referenced by foldMemoryOperand().
| virtual MachineInstr* llvm::TargetInstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, | |
| MachineInstr * | MI, | |||
| const SmallVectorImpl< unsigned > & | Ops, | |||
| MachineInstr * | LoadMI | |||
| ) | const [inline, protected, virtual] |
foldMemoryOperandImpl - Target-dependent implementation for foldMemoryOperand. Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction.
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::MipsInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, and llvm::X86InstrInfo.
Definition at line 335 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::canFoldMemoryOperand | ( | const MachineInstr * | MI, | |
| const SmallVectorImpl< unsigned > & | Ops | |||
| ) | const [inline, virtual] |
canFoldMemoryOperand - Returns true for the specified load / store if folding is possible.
Reimplemented in llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::PPCInstrInfo, and llvm::X86InstrInfo.
Definition at line 346 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::unfoldMemoryOperand | ( | MachineFunction & | MF, | |
| MachineInstr * | MI, | |||
| unsigned | Reg, | |||
| bool | UnfoldLoad, | |||
| bool | UnfoldStore, | |||
| SmallVectorImpl< MachineInstr * > & | NewMIs | |||
| ) | const [inline, virtual] |
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. If this is possible, returns true as well as the new instructions by reference.
Reimplemented in llvm::X86InstrInfo.
Definition at line 354 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::unfoldMemoryOperand | ( | SelectionDAG & | DAG, | |
| SDNode * | N, | |||
| SmallVectorImpl< SDNode * > & | NewNodes | |||
| ) | const [inline, virtual] |
| virtual unsigned llvm::TargetInstrInfo::getOpcodeAfterMemoryUnfold | ( | unsigned | Opc, | |
| bool | UnfoldLoad, | |||
| bool | UnfoldStore | |||
| ) | const [inline, virtual] |
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. It returns zero if the specified unfolding is not possible.
Reimplemented in llvm::X86InstrInfo.
Definition at line 369 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::BlockHasNoFallThrough | ( | const MachineBasicBlock & | MBB | ) | const [inline, virtual] |
BlockHasNoFallThrough - Return true if the specified block does not fall-through into its successor block. This is primarily used when a branch is unanalyzable. It is useful for things like unconditional indirect branches (jump tables).
Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::SPUInstrInfo, llvm::MipsInstrInfo, llvm::PPCInstrInfo, llvm::X86InstrInfo, and llvm::XCoreInstrInfo.
Definition at line 378 of file TargetInstrInfo.h.