llvm::TargetInstrDesc Class Reference
#include <TargetInstrDesc.h>
Detailed Description
TargetInstrDesc - Describe properties that are true of each instruction in the target description file. This captures information about side effects, register use and many other things. There is one instance of this struct for each target instruction class, and the MachineInstr class points to this struct directly to describe itself.Definition at line 108 of file TargetInstrDesc.h.
Member Function Documentation
| int llvm::TargetInstrDesc::getOperandConstraint | ( | unsigned | OpNum, | |
| TOI::OperandConstraint | Constraint | |||
| ) | const [inline] |
getOperandConstraint - Returns the value of the specific constraint if it is set. Returns -1 if it is not set.
Definition at line 124 of file TargetInstrDesc.h.
References llvm::TargetOperandInfo::Constraints, Constraints, NumOperands, and OpInfo.
Referenced by llvm::LiveIntervals::addIntervalsForSpills(), llvm::X86InstrInfo::canFoldMemoryOperand(), llvm::TargetInstrInfoImpl::CommuteChangesDestination(), llvm::TargetInstrInfoImpl::commuteInstruction(), llvm::PPCInstrInfo::commuteInstruction(), llvm::X86InstrInfo::determineREX(), FilterFoldedOps(), findTiedToSrcOperand(), GetInstSizeWithDesc(), llvm::MachineInstr::isRegReDefinedByTwoAddr(), isTwoAddrUse(), and UpdateKills().
| int TargetInstrDesc::findTiedToSrcOperand | ( | unsigned | OpNum | ) | const |
findTiedToSrcOperand - Returns the operand that is tied to the specified dest operand. Returns -1 if there isn't one.
findTiedToSrcOperand - Returns the operand that is tied to the specified dest operand. Returns -1 if there isn't one.
Definition at line 21 of file TargetInstrInfo.cpp.
References getNumOperands(), getOperandConstraint(), and llvm::TOI::TIED_TO.
Referenced by llvm::RegScavenger::backward(), and llvm::RegScavenger::forward().
| unsigned llvm::TargetInstrDesc::getOpcode | ( | ) | const [inline] |
getOpcode - Return the opcode number for this descriptor.
Definition at line 139 of file TargetInstrDesc.h.
References Opcode.
Referenced by llvm::X86InstrInfo::GetInstSizeInBytes().
| const char* llvm::TargetInstrDesc::getName | ( | ) | const [inline] |
getName - Return the name of the record in the .td file for this instruction, for example "ADD8ri".
Definition at line 145 of file TargetInstrDesc.h.
References Name.
Referenced by llvm::SDNode::getOperationName(), and llvm::MachineInstr::print().
| unsigned llvm::TargetInstrDesc::getNumOperands | ( | ) | const [inline] |
getNumOperands - Return the number of declared MachineOperands for this MachineInstruction. Note that variadic (isVariadic() returns true) instructions may have additional operands at the end of the list, and note that the machine instruction may include implicit register def/uses as well.
Definition at line 154 of file TargetInstrDesc.h.
References NumOperands.
Referenced by llvm::ScheduleDAGInstrs::BuildSchedGraph(), llvm::X86InstrInfo::canFoldMemoryOperand(), llvm::ARMInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::determineREX(), llvm::ScheduleDAGSDNodes::EmitNode(), findTiedToSrcOperand(), llvm::X86InstrInfo::foldMemoryOperandImpl(), FuseTwoAddrInst(), getInstrOperandRegClass(), llvm::ARMInstrInfo::GetInstSizeInBytes(), GetInstSizeWithDesc(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MipsInstrInfo::InsertBranch(), llvm::ARMInstrInfo::isMoveInstr(), llvm::MachineInstr::isRegReDefinedByTwoAddr(), isTwoAddrUse(), and UpdateKills().
| unsigned llvm::TargetInstrDesc::getNumDefs | ( | ) | const [inline] |
getNumDefs - Return the number of MachineOperands that are register definitions. Register definitions always occur at the start of the machine operand list. This is the number of "outs" in the .td file, and does not include implicit defs.
Definition at line 162 of file TargetInstrDesc.h.
References NumDefs.
Referenced by CheckForPhysRegDependency(), llvm::ScheduleDAGSDNodes::EmitNode(), llvm::FastISel::FastEmitInst_extractsubreg(), llvm::FastISel::FastEmitInst_i(), llvm::FastISel::FastEmitInst_r(), llvm::FastISel::FastEmitInst_rf(), llvm::FastISel::FastEmitInst_ri(), llvm::FastISel::FastEmitInst_rr(), llvm::FastISel::FastEmitInst_rri(), getPhysicalRegisterVT(), and llvm::X86InstrInfo::unfoldMemoryOperand().
| bool llvm::TargetInstrDesc::isVariadic | ( | ) | const [inline] |
isVariadic - Return true if this instruction can have a variable number of operands. In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).
Definition at line 170 of file TargetInstrDesc.h.
References Flags, and llvm::TID::Variadic.
Referenced by llvm::ScheduleDAGSDNodes::EmitNode(), getInstrOperandRegClass(), GetInstSizeWithDesc(), and llvm::MachineInstr::getNumExplicitOperands().
| bool llvm::TargetInstrDesc::hasOptionalDef | ( | ) | const [inline] |
hasOptionalDef - Set if this instruction has an optional definition, e.g. ARM instructions which can set condition code if 's' bit is set.
Definition at line 176 of file TargetInstrDesc.h.
References Flags, and llvm::TID::HasOptionalDef.
Referenced by llvm::ARMInstrInfo::DefinesPredicate().
| const unsigned* llvm::TargetInstrDesc::getImplicitUses | ( | ) | const [inline] |
getImplicitUses - Return a list of registers that are potentially read by any instance of this machine instruction. For example, on X86, the "adc" instruction adds two register operands and adds the carry bit in from the flags register. In this case, the instruction is marked as implicitly reading the flags. Likewise, the variable shift instruction on X86 is marked as implicitly reading the 'CL' register, which it always does.
This method returns null if the instruction has no implicit uses.
Definition at line 189 of file TargetInstrDesc.h.
References ImplicitUses.
| const unsigned* llvm::TargetInstrDesc::getImplicitDefs | ( | ) | const [inline] |
getImplicitDefs - Return a list of registers that are potentially written by any instance of this machine instruction. For example, on X86, many instructions implicitly set the flags register. In this case, they are marked as setting the FLAGS. Likewise, many instructions always deposit their result in a physical register. For example, the X86 divide instruction always deposits the quotient and remainder in the EAX/EDX registers. For that instruction, this will return a list containing the EAX/EDX/EFLAGS registers.
This method returns null if the instruction has no implicit defs.
Definition at line 203 of file TargetInstrDesc.h.
References ImplicitDefs.
Referenced by llvm::ARMInstrInfo::DefinesPredicate(), llvm::ScheduleDAGSDNodes::EmitNode(), and getPhysicalRegisterVT().
| const TargetRegisterClass** llvm::TargetInstrDesc::getRegClassBarriers | ( | ) | const [inline] |
getRegClassBarriers - Return a list of register classes that are completely clobbered by this machine instruction. For example, on X86 the call instructions will completely clobber all the registers in the fp stack and XMM classes.
This method returns null if the instruction doesn't completely clobber any register class.
Definition at line 214 of file TargetInstrDesc.h.
References RCBarriers.
| unsigned llvm::TargetInstrDesc::getSchedClass | ( | ) | const [inline] |
getSchedClass - Return the scheduling class for this instruction. The scheduling class is an index into the InstrItineraryData table. This returns zero if there is no known scheduling information for the instruction.
Definition at line 223 of file TargetInstrDesc.h.
References SchedClass.
Referenced by llvm::ScheduleDAGInstrs::ComputeLatency().
| bool llvm::TargetInstrDesc::isReturn | ( | ) | const [inline] |
Definition at line 227 of file TargetInstrDesc.h.
References Flags, and llvm::TID::Return.
Referenced by llvm::LiveVariables::runOnMachineFunction().
| bool llvm::TargetInstrDesc::isCall | ( | ) | const [inline] |
Definition at line 231 of file TargetInstrDesc.h.
References llvm::TID::Call, and Flags.
Referenced by llvm::ScheduleDAGInstrs::BuildSchedGraph(), EstimateRuntime(), llvm::MachineInstr::hasVolatileMemoryRef(), IsBetterFallthrough(), and llvm::MachineInstr::isSafeToMove().
| bool llvm::TargetInstrDesc::isBarrier | ( | ) | const [inline] |
isBarrier - Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions.
Definition at line 238 of file TargetInstrDesc.h.
References llvm::TID::Barrier, and Flags.
Referenced by isConditionalBranch(), isUnconditionalBranch(), llvm::X86InstrInfo::isUnpredicatedTerminator(), and llvm::TargetInstrInfo::isUnpredicatedTerminator().
| bool llvm::TargetInstrDesc::isTerminator | ( | ) | const [inline] |
isTerminator - Returns true if this instruction part of the terminator for a basic block. Typically this is things like return and branch instructions.
Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.
Definition at line 248 of file TargetInstrDesc.h.
References Flags, and llvm::TID::Terminator.
Referenced by llvm::ScheduleDAGInstrs::BuildSchedGraph(), llvm::MachineInstr::isSafeToMove(), llvm::X86InstrInfo::isUnpredicatedTerminator(), and llvm::TargetInstrInfo::isUnpredicatedTerminator().
| bool llvm::TargetInstrDesc::isBranch | ( | ) | const [inline] |
isBranch - Returns true if this is a conditional, unconditional, or indirect branch. Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information.
Definition at line 256 of file TargetInstrDesc.h.
References llvm::TID::Branch, and Flags.
Referenced by llvm::MipsInstrInfo::AnalyzeBranch(), isConditionalBranch(), isUnconditionalBranch(), llvm::X86InstrInfo::isUnpredicatedTerminator(), and llvm::TargetInstrInfo::isUnpredicatedTerminator().
| bool llvm::TargetInstrDesc::isIndirectBranch | ( | ) | const [inline] |
isIndirectBranch - Return true if this is an indirect branch, such as a branch through a register.
Definition at line 262 of file TargetInstrDesc.h.
References Flags, and llvm::TID::IndirectBranch.
Referenced by isConditionalBranch(), and isUnconditionalBranch().
| bool llvm::TargetInstrDesc::isConditionalBranch | ( | ) | const [inline] |
isConditionalBranch - Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.
Definition at line 270 of file TargetInstrDesc.h.
References isBarrier(), isBranch(), and isIndirectBranch().
| bool llvm::TargetInstrDesc::isUnconditionalBranch | ( | ) | const [inline] |
isUnconditionalBranch - Return true if this is a branch which always transfers control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.
Definition at line 278 of file TargetInstrDesc.h.
References isBarrier(), isBranch(), and isIndirectBranch().
| bool llvm::TargetInstrDesc::isPredicable | ( | ) | const [inline] |
values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.
Definition at line 286 of file TargetInstrDesc.h.
References Flags, and llvm::TID::Predicable.
Referenced by llvm::MachineInstr::copyPredicates(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::ARMInstrInfo::GetInstSizeInBytes(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), and llvm::TargetInstrInfoImpl::PredicateInstruction().
| bool llvm::TargetInstrDesc::isNotDuplicable | ( | ) | const [inline] |
isNotDuplicable - Return true if this instruction cannot be safely duplicated. For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.
Definition at line 293 of file TargetInstrDesc.h.
References Flags, and llvm::TID::NotDuplicable.
| bool llvm::TargetInstrDesc::hasDelaySlot | ( | ) | const [inline] |
hasDelaySlot - Returns true if the specified instruction has a delay slot which must be filled by the code generator.
Definition at line 299 of file TargetInstrDesc.h.
References llvm::TID::DelaySlot, and Flags.
| bool llvm::TargetInstrDesc::canFoldAsLoad | ( | ) | const [inline] |
canFoldAsLoad - Return true for instructions that can be folded as memory operands in other instructions. The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.
Definition at line 311 of file TargetInstrDesc.h.
References Flags, and llvm::TID::FoldableAsLoad.
Referenced by llvm::LiveIntervals::addIntervalsForSpills(), and llvm::TargetInstrInfo::foldMemoryOperand().
| bool llvm::TargetInstrDesc::mayLoad | ( | ) | const [inline] |
mayLoad - Return true if this instruction could possibly read memory. Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.
Definition at line 322 of file TargetInstrDesc.h.
References Flags, and llvm::TID::MayLoad.
Referenced by llvm::addFrameReference(), llvm::ScheduleDAGInstrs::BuildSchedGraph(), llvm::ScheduleDAGInstrs::ComputeLatency(), llvm::ARMRegisterInfo::eliminateFrameIndex(), EstimateRuntime(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::MachineInstr::hasVolatileMemoryRef(), and llvm::MachineInstr::isSafeToMove().
| bool llvm::TargetInstrDesc::mayStore | ( | ) | const [inline] |
mayStore - Return true if this instruction could possibly modify memory. Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.
Definition at line 331 of file TargetInstrDesc.h.
References Flags, and llvm::TID::MayStore.
Referenced by llvm::addFrameReference(), llvm::ScheduleDAGInstrs::BuildSchedGraph(), llvm::ARMInstrInfo::convertToThreeAddress(), llvm::ARMRegisterInfo::eliminateFrameIndex(), EstimateRuntime(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::MachineInstr::hasVolatileMemoryRef(), and llvm::MachineInstr::isSafeToMove().
| bool llvm::TargetInstrDesc::hasUnmodeledSideEffects | ( | ) | const [inline] |
hasUnmodeledSideEffects - Return true if this instruction has side effects that are not modeled by other flags. This does not return true for instructions whose effects are captured by:
1. Their operand list and implicit definition/use list. Register use/def info is explicit for instructions. 2. Memory accesses. Use mayLoad/mayStore. 3. Calling, branching, returning: use isCall/isReturn/isBranch.
Examples of side effects would be modifying 'invisible' machine state like a control register, flushing a cache, modifying a register invisible to LLVM, etc.
Definition at line 348 of file TargetInstrDesc.h.
References Flags, and llvm::TID::UnmodeledSideEffects.
Referenced by llvm::ScheduleDAGInstrs::BuildSchedGraph(), llvm::MachineInstr::hasVolatileMemoryRef(), and llvm::MachineInstr::isSafeToMove().
| bool llvm::TargetInstrDesc::isCommutable | ( | ) | const [inline] |
isCommutable - Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.
Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.
Definition at line 366 of file TargetInstrDesc.h.
References llvm::TID::Commutable, and Flags.
| bool llvm::TargetInstrDesc::isConvertibleTo3Addr | ( | ) | const [inline] |
isConvertibleTo3Addr - Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.
If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).
Definition at line 384 of file TargetInstrDesc.h.
References llvm::TID::ConvertibleTo3Addr, and Flags.
| bool llvm::TargetInstrDesc::usesCustomDAGSchedInsertionHook | ( | ) | const [inline] |
usesCustomDAGSchedInsertionHook - Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.
If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.
Definition at line 396 of file TargetInstrDesc.h.
References Flags, and llvm::TID::UsesCustomDAGSchedInserter.
Referenced by llvm::ScheduleDAGSDNodes::EmitNode().
| bool llvm::TargetInstrDesc::isRematerializable | ( | ) | const [inline] |
isRematerializable - Returns true if this instruction is a candidate for remat. This flag is deprecated, please don't use it anymore. If this flag is set, the isReallyTriviallyReMaterializable() method is called to verify the instruction is really rematable.
Definition at line 404 of file TargetInstrDesc.h.
References Flags, and llvm::TID::Rematerializable.
Referenced by llvm::TargetInstrInfo::isTriviallyReMaterializable().
| bool llvm::TargetInstrDesc::isAsCheapAsAMove | ( | ) | const [inline] |
isAsCheapAsAMove - Returns true if this instruction has the same cost (or less) than a move instruction. This is useful during certain types of rematerializations (e.g., during two-address conversion) where we would like to remat the instruction, but not if it costs more than moving the instruction into the appropriate register.
Definition at line 413 of file TargetInstrDesc.h.
References llvm::TID::CheapAsAMove, and Flags.
Member Data Documentation
Definition at line 110 of file TargetInstrDesc.h.
Referenced by GetInstSizeWithDesc(), getOpcode(), and llvm::MachineInstr::getOpcode().
Definition at line 111 of file TargetInstrDesc.h.
Referenced by getNumOperands(), and getOperandConstraint().
| const char* llvm::TargetInstrDesc::Name |
Definition at line 115 of file TargetInstrDesc.h.
Referenced by canFoldAsLoad(), hasDelaySlot(), hasOptionalDef(), hasUnmodeledSideEffects(), isAsCheapAsAMove(), isBarrier(), isBranch(), isCall(), isCommutable(), isConvertibleTo3Addr(), isIndirectBranch(), isNotDuplicable(), isPredicable(), isRematerializable(), isReturn(), isTerminator(), isVariadic(), mayLoad(), mayStore(), and usesCustomDAGSchedInsertionHook().
Definition at line 116 of file TargetInstrDesc.h.
Referenced by llvm::ARMInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::determineREX(), llvm::ARMRegisterInfo::eliminateFrameIndex(), llvm::X86InstrInfo::getBaseOpcodeFor(), llvm::ARMInstrInfo::GetInstSizeInBytes(), GetInstSizeWithDesc(), llvm::ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(), and llvm::X86InstrInfo::sizeOfImm().
Definition at line 118 of file TargetInstrDesc.h.
Referenced by CheckForPhysRegDependency(), llvm::FastISel::FastEmitInst_extractsubreg(), llvm::FastISel::FastEmitInst_i(), llvm::FastISel::FastEmitInst_r(), llvm::FastISel::FastEmitInst_rf(), llvm::FastISel::FastEmitInst_ri(), llvm::FastISel::FastEmitInst_rr(), llvm::FastISel::FastEmitInst_rri(), getImplicitDefs(), and getPhysicalRegisterVT().
Definition at line 120 of file TargetInstrDesc.h.
Referenced by llvm::ScheduleDAGInstrs::BuildSchedGraph(), llvm::MachineInstr::copyPredicates(), llvm::MachineInstr::findFirstPredOperandIdx(), getInstrOperandRegClass(), getOperandConstraint(), llvm::TargetInstrInfoImpl::PredicateInstruction(), and llvm::X86InstrInfo::unfoldMemoryOperand().
The documentation for this class was generated from the following files:
1.5.6