llvm::SelectionDAGLowering Class Reference
#include <SelectionDAGBuild.h>
Public Member Functions | |
| SelectionDAGLowering (SelectionDAG &dag, TargetLowering &tli, FunctionLoweringInfo &funcinfo) | |
| void | init (GCFunctionInfo *gfi, AliasAnalysis &aa) |
| void | clear () |
| SDValue | getRoot () |
| SDValue | getControlRoot () |
| void | CopyValueToVirtualRegister (Value *V, unsigned Reg) |
| void | visit (Instruction &I) |
| void | visit (unsigned Opcode, User &I) |
| void | setCurrentBasicBlock (MachineBasicBlock *MBB) |
| SDValue | getValue (const Value *V) |
| void | setValue (const Value *V, SDValue NewN) |
| void | GetRegistersForValue (SDISelAsmOperandInfo &OpInfo, std::set< unsigned > &OutputRegs, std::set< unsigned > &InputRegs) |
| void | FindMergedConditions (Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, unsigned Opc) |
| FindMergedConditions - If Cond is an expression like. | |
| bool | ShouldEmitAsBranches (const std::vector< CaseBlock > &Cases) |
| bool | isExportableFromCurrentBlock (Value *V, const BasicBlock *FromBB) |
| void | ExportFromCurrentBlock (Value *V) |
| void | LowerCallTo (CallSite CS, SDValue Callee, bool IsTailCall, MachineBasicBlock *LandingPad=NULL) |
| void | visitSwitchCase (CaseBlock &CB) |
| void | visitBitTestHeader (BitTestBlock &B) |
| void | visitBitTestCase (MachineBasicBlock *NextMBB, unsigned Reg, BitTestCase &B) |
| visitBitTestCase - this function produces one "bit test" | |
| void | visitJumpTable (JumpTable &JT) |
| visitJumpTable - Emit JumpTable node in the current MBB | |
| void | visitJumpTableHeader (JumpTable &JT, JumpTableHeader &JTH) |
Public Attributes | |
| TargetLowering & | TLI |
| SelectionDAG & | DAG |
| const TargetData * | TD |
| AliasAnalysis * | AA |
| std::vector< CaseBlock > | SwitchCases |
| std::vector< JumpTableBlock > | JTCases |
| std::vector< BitTestBlock > | BitTestCases |
| std::vector< std::pair < MachineInstr *, unsigned > > | PHINodesToUpdate |
| DenseMap< Constant *, unsigned > | ConstantsOut |
| FunctionLoweringInfo & | FuncInfo |
| GCFunctionInfo * | GFI |
| GFI - Garbage collection metadata for the function. | |
Classes | |
| struct | BitTestBlock |
| struct | BitTestCase |
| struct | Case |
| struct | CaseBits |
| struct | CaseBitsCmp |
| struct | CaseBlock |
| struct | CaseCmp |
| struct | CaseRec |
| struct | JumpTable |
| struct | JumpTableHeader |
Detailed Description
SelectionDAGLowering - This is the common target-independent lowering implementation that is parameterized by a TargetLowering object. Also, targets can overload any lowering method.Definition at line 164 of file SelectionDAGBuild.h.
Constructor & Destructor Documentation
| llvm::SelectionDAGLowering::SelectionDAGLowering | ( | SelectionDAG & | dag, | |
| TargetLowering & | tli, | |||
| FunctionLoweringInfo & | funcinfo | |||
| ) | [inline] |
Definition at line 357 of file SelectionDAGBuild.h.
Member Function Documentation
| void SelectionDAGLowering::init | ( | GCFunctionInfo * | gfi, | |
| AliasAnalysis & | aa | |||
| ) |
Definition at line 685 of file SelectionDAGBuild.cpp.
References AA, DAG, llvm::SelectionDAG::getTarget(), llvm::TargetMachine::getTargetData(), GFI, and TD.
Referenced by llvm::SelectionDAGISel::runOnFunction().
| void SelectionDAGLowering::clear | ( | ) |
clear - Clear out the curret SelectionDAG and the associated state and prepare this SelectionDAGLowering object to be used for a new block. This doesn't clear out information about additional blocks that are needed to complete switch lowering or PHI node updating; that information is cleared out as it is consumed.
clear - Clear out the curret SelectionDAG and the associated state and prepare this SelectionDAGLowering object to be used for a new block. This doesn't clear out information about additional blocks that are needed to complete switch lowering or PHI node updating; that information is cleared out as it is consumed.
Definition at line 697 of file SelectionDAGBuild.cpp.
References llvm::SelectionDAG::clear(), and DAG.
| SDValue SelectionDAGLowering::getRoot | ( | ) |
getRoot - Return the current virtual root of the Selection DAG, flushing any PendingLoad items. This must be done before emitting a store or any other node that may need to be ordered after any prior load instructions.
getRoot - Return the current virtual root of the Selection DAG, flushing any PendingLoad items. This must be done before emitting a store or any other node that may need to be ordered after any prior load instructions.
Definition at line 709 of file SelectionDAGBuild.cpp.
References DAG, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRoot(), llvm::MVT::Other, Root, llvm::SelectionDAG::setRoot(), and llvm::ISD::TokenFactor.
Referenced by LowerCallTo().
| SDValue SelectionDAGLowering::getControlRoot | ( | ) |
getControlRoot - Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports items. It is necessary to do this before emitting a terminator instruction.
getControlRoot - Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports items. It is necessary to do this before emitting a terminator instruction.
Definition at line 732 of file SelectionDAGBuild.cpp.
References DAG, llvm::ISD::EntryToken, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getRoot(), llvm::MVT::Other, Root, llvm::SelectionDAG::setRoot(), and llvm::ISD::TokenFactor.
Referenced by LowerCallTo(), visitBitTestCase(), visitBitTestHeader(), visitJumpTable(), visitJumpTableHeader(), and visitSwitchCase().
Definition at line 5377 of file SelectionDAGBuild.cpp.
References llvm::ISD::CopyFromReg, DAG, llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::Value::getType(), getValue(), llvm::TargetRegisterInfo::isPhysicalRegister(), and TLI.
Referenced by ExportFromCurrentBlock().
| void SelectionDAGLowering::visit | ( | Instruction & | I | ) |
Definition at line 759 of file SelectionDAGBuild.cpp.
References llvm::Instruction::getOpcode().
Referenced by getValue().
Definition at line 763 of file SelectionDAGBuild.cpp.
| void llvm::SelectionDAGLowering::setCurrentBasicBlock | ( | MachineBasicBlock * | MBB | ) | [inline] |
Definition at line 391 of file SelectionDAGBuild.h.
Definition at line 790 of file SelectionDAGBuild.cpp.
References AI, llvm::SmallVectorImpl< T >::assign(), llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, CI, ComputeValueVTs(), CP, DAG, FuncInfo, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SequentialType::getElementType(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getFrameIndex(), llvm::SelectionDAG::getGlobalAddress(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::VectorType::getNumElements(), llvm::SDNode::getNumValues(), llvm::Constant::getOperand(), llvm::TargetLowering::getPointerTy(), llvm::Value::getType(), llvm::TargetLowering::getValueType(), GV, llvm::Attribute::InReg, llvm::Type::isAggregateType(), llvm::MVT::isFloatingPoint(), Op, llvm::SmallVectorImpl< T >::push_back(), llvm::SmallVectorImpl< T >::size(), llvm::FunctionLoweringInfo::StaticAllocaMap, TLI, llvm::ISD::UNDEF, Val, llvm::FunctionLoweringInfo::ValueMap, visit(), and VT.
Referenced by CopyValueToVirtualRegister(), LowerCallTo(), visitBitTestHeader(), visitJumpTableHeader(), and visitSwitchCase().
Definition at line 395 of file SelectionDAGBuild.h.
References llvm::SDValue::getNode().
Referenced by LowerCallTo().
| void SelectionDAGLowering::GetRegistersForValue | ( | SDISelAsmOperandInfo & | OpInfo, | |
| std::set< unsigned > & | OutputRegs, | |||
| std::set< unsigned > & | InputRegs | |||
| ) |
GetRegistersForValue - Assign registers (virtual or physical) for the specified operand. We prefer to assign virtual registers, to allow the register allocator handle the assignment process. However, if the asm uses features that we can't model on machineinstrs, we have SDISel do the allocation. This produces generally horrible, but correct, code.
OpInfo describes the operand. Input and OutputRegs are the set of already allocated physical registers.
Definition at line 4479 of file SelectionDAGBuild.cpp.
References llvm::SDISelAsmOperandInfo::AssignedRegs, llvm::TargetLowering::AsmOperandInfo::ConstraintCode, llvm::TargetLowering::AsmOperandInfo::ConstraintVT, llvm::MachineRegisterInfo::createVirtualRegister(), DAG, llvm::SelectionDAG::getMachineFunction(), llvm::TargetLowering::getNumRegisters(), llvm::TargetLowering::getRegClassForInlineAsmConstraint(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetMachine::getRegisterInfo(), llvm::SelectionDAG::getTarget(), llvm::InlineAsm::ConstraintInfo::hasMatchingInput, isAllocatableRegister(), llvm::InlineAsm::isClobber, llvm::InlineAsm::isInput, llvm::InlineAsm::isOutput, llvm::SDISelAsmOperandInfo::MarkAllocatedRegs(), MF, llvm::MVT::Other, llvm::SmallVectorImpl< T >::push_back(), RegInfo, TLI, llvm::InlineAsm::ConstraintInfo::Type, and llvm::TargetRegisterClass::vt_begin().
| void SelectionDAGLowering::FindMergedConditions | ( | Value * | Cond, | |
| MachineBasicBlock * | TBB, | |||
| MachineBasicBlock * | FBB, | |||
| MachineBasicBlock * | CurBB, | |||
| unsigned | Opc | |||
| ) |
FindMergedConditions - If Cond is an expression like.
Definition at line 1000 of file SelectionDAGBuild.cpp.
References And(), BB, BBI, llvm::MachineFunction::CreateMachineBasicBlock(), DAG, llvm::dyn_cast(), llvm::CmpInst::FCMP_FALSE, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_TRUE, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::FiniteOnlyFPMath(), llvm::MachineBasicBlock::getBasicBlock(), llvm::SelectionDAG::getMachineFunction(), llvm::Instruction::getOpcode(), llvm::User::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::Instruction::getParent(), llvm::ConstantInt::getTrue(), llvm::Value::hasOneUse(), IC, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, InBlock(), llvm::MachineFunction::insert(), isExportableFromCurrentBlock(), MF, llvm::APIntOps::Or(), llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETTRUE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, and SwitchCases.
| bool SelectionDAGLowering::ShouldEmitAsBranches | ( | const std::vector< CaseBlock > & | Cases | ) |
If the set of cases should be emitted as a series of branches, return true. If we should emit this as a bunch of and/or'd together conditions, return false.
Definition at line 1127 of file SelectionDAGBuild.cpp.
| bool SelectionDAGLowering::isExportableFromCurrentBlock | ( | Value * | V, | |
| const BasicBlock * | FromBB | |||
| ) |
Definition at line 966 of file SelectionDAGBuild.cpp.
References FuncInfo, llvm::Function::getEntryBlock(), llvm::BasicBlock::getParent(), and llvm::FunctionLoweringInfo::isExportedInst().
Referenced by FindMergedConditions().
| void SelectionDAGLowering::ExportFromCurrentBlock | ( | Value * | V | ) |
ExportFromCurrentBlock - If this condition isn't known to be exported from the current basic block, add it to ValueMap now so that we'll get a CopyTo/FromReg.
Definition at line 955 of file SelectionDAGBuild.cpp.
References CopyValueToVirtualRegister(), FuncInfo, llvm::FunctionLoweringInfo::InitializeRegForValue(), llvm::FunctionLoweringInfo::isExportedInst(), and Reg.
| void SelectionDAGLowering::LowerCallTo | ( | CallSite | CS, | |
| SDValue | Callee, | |||
| bool | IsTailCall, | |||
| MachineBasicBlock * | LandingPad = NULL | |||
| ) |
Definition at line 4086 of file SelectionDAGBuild.cpp.
References llvm::TargetLowering::ArgListEntry::Alignment, llvm::CallSite::arg_begin(), llvm::CallSite::arg_end(), llvm::CallSite::arg_size(), BeginLabel, llvm::Attribute::ByVal, DAG, llvm::ISD::EH_LABEL, EndLabel, Entry, llvm::CallSite::getCalledValue(), llvm::CallSite::getCallingConv(), getControlRoot(), llvm::SequentialType::getElementType(), llvm::CallSite::getInstruction(), llvm::SelectionDAG::getLabel(), llvm::SelectionDAG::getMachineModuleInfo(), llvm::CallSite::getParamAlignment(), getRoot(), llvm::CallSite::getType(), llvm::Value::getType(), getValue(), llvm::Attribute::InReg, llvm::TargetLowering::ArgListEntry::isByVal, llvm::TargetLowering::ArgListEntry::isInReg, llvm::TargetLowering::ArgListEntry::isNest, llvm::TargetLowering::ArgListEntry::isSExt, llvm::TargetLowering::ArgListEntry::isSRet, llvm::TargetLowering::ArgListEntry::isZExt, llvm::TargetLowering::LowerCallTo(), llvm::Attribute::Nest, llvm::TargetLowering::ArgListEntry::Node, llvm::CallSite::paramHasAttr(), llvm::PerformTailCallOpt, llvm::SelectionDAG::setRoot(), setValue(), llvm::Attribute::SExt, llvm::Attribute::StructRet, TLI, llvm::TargetLowering::ArgListEntry::Ty, llvm::Type::VoidTy, and llvm::Attribute::ZExt.
| void SelectionDAGLowering::visitSwitchCase | ( | CaseBlock & | CB | ) |
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resulting from lowering a switch instruction.
Definition at line 1225 of file SelectionDAGBuild.cpp.
References llvm::MachineBasicBlock::addSuccessor(), llvm::ISD::BR, llvm::ISD::BRCOND, BrCond, DAG, llvm::MachineFunction::end(), llvm::SelectionDAG::getBasicBlock(), llvm::SelectionDAG::getConstant(), getControlRoot(), llvm::ConstantInt::getFalse(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::SelectionDAG::getSetCC(), llvm::ConstantInt::getTrue(), getValue(), llvm::SDValue::getValueType(), High, llvm::MVT::i1, Low, llvm::MVT::Other, llvm::MachineBasicBlock::removeSuccessor(), llvm::ISD::SETEQ, llvm::ISD::SETLE, llvm::SelectionDAG::setRoot(), llvm::ISD::SETULE, llvm::ISD::SUB, std::swap(), and llvm::ISD::XOR.
| void SelectionDAGLowering::visitBitTestHeader | ( | BitTestBlock & | B | ) |
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests"
Definition at line 1362 of file SelectionDAGBuild.cpp.
References llvm::MachineBasicBlock::addSuccessor(), llvm::MVT::bitsGT(), llvm::ISD::BR, llvm::ISD::BRCOND, DAG, llvm::MachineFunction::end(), FuncInfo, llvm::SelectionDAG::getBasicBlock(), llvm::SelectionDAG::getConstant(), getControlRoot(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getNode(), llvm::MachineBasicBlock::getParent(), llvm::TargetLowering::getPointerTy(), llvm::SelectionDAG::getSetCC(), llvm::TargetLowering::getSetCCResultType(), llvm::TargetLowering::getShiftAmountTy(), getValue(), llvm::SDValue::getValueType(), llvm::FunctionLoweringInfo::MakeReg(), MBB, llvm::MVT::Other, llvm::SelectionDAG::setRoot(), llvm::ISD::SETUGT, llvm::ISD::SHL, llvm::ISD::SUB, TLI, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
| void SelectionDAGLowering::visitBitTestCase | ( | MachineBasicBlock * | NextMBB, | |
| unsigned | Reg, | |||
| BitTestCase & | B | |||
| ) |
visitBitTestCase - this function produces one "bit test"
Definition at line 1414 of file SelectionDAGBuild.cpp.
References llvm::MachineBasicBlock::addSuccessor(), llvm::ISD::AND, llvm::ISD::BR, llvm::ISD::BRCOND, DAG, llvm::MachineFunction::end(), llvm::SelectionDAG::getBasicBlock(), llvm::SelectionDAG::getConstant(), getControlRoot(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getNode(), llvm::MachineBasicBlock::getParent(), llvm::TargetLowering::getPointerTy(), llvm::SelectionDAG::getSetCC(), llvm::TargetLowering::getSetCCResultType(), llvm::MVT::Other, llvm::ISD::SETNE, llvm::SelectionDAG::setRoot(), and TLI.
| void SelectionDAGLowering::visitJumpTable | ( | JumpTable & | JT | ) |
visitJumpTable - Emit JumpTable node in the current MBB
Definition at line 1297 of file SelectionDAGBuild.cpp.
References llvm::ISD::BR_JT, DAG, getControlRoot(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getJumpTable(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getPointerTy(), llvm::SDValue::getValue(), Index, llvm::MVT::Other, llvm::SelectionDAG::setRoot(), and TLI.
| void SelectionDAGLowering::visitJumpTableHeader | ( | JumpTable & | JT, | |
| JumpTableHeader & | JTH | |||
| ) |
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from switch case.
Definition at line 1310 of file SelectionDAGBuild.cpp.
References llvm::MVT::bitsGT(), llvm::ISD::BR, llvm::ISD::BRCOND, BrCond, llvm::X86ISD::CMP, DAG, llvm::MachineFunction::end(), FuncInfo, llvm::SelectionDAG::getBasicBlock(), llvm::SelectionDAG::getConstant(), getControlRoot(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getNode(), llvm::MachineBasicBlock::getParent(), llvm::TargetLowering::getPointerTy(), llvm::SelectionDAG::getSetCC(), llvm::TargetLowering::getSetCCResultType(), getValue(), llvm::SDValue::getValueType(), llvm::FunctionLoweringInfo::MakeReg(), llvm::MVT::Other, llvm::SelectionDAG::setRoot(), llvm::ISD::SETUGT, llvm::ISD::SUB, TLI, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Member Data Documentation
Definition at line 329 of file SelectionDAGBuild.h.
Referenced by CopyValueToVirtualRegister(), GetRegistersForValue(), getValue(), LowerCallTo(), visitBitTestCase(), visitBitTestHeader(), visitJumpTable(), and visitJumpTableHeader().
Definition at line 330 of file SelectionDAGBuild.h.
Referenced by clear(), CopyValueToVirtualRegister(), FindMergedConditions(), getControlRoot(), GetRegistersForValue(), getRoot(), getValue(), init(), LowerCallTo(), visitBitTestCase(), visitBitTestHeader(), visitJumpTable(), visitJumpTableHeader(), and visitSwitchCase().
| std::vector<CaseBlock> llvm::SelectionDAGLowering::SwitchCases |
SwitchCases - Vector of CaseBlock structures used to communicate SwitchInst code generation information.
Definition at line 336 of file SelectionDAGBuild.h.
Referenced by FindMergedConditions().
| std::vector<JumpTableBlock> llvm::SelectionDAGLowering::JTCases |
JTCases - Vector of JumpTable structures used to communicate SwitchInst code generation information.
Definition at line 339 of file SelectionDAGBuild.h.
| std::vector<BitTestBlock> llvm::SelectionDAGLowering::BitTestCases |
BitTestCases - Vector of BitTestBlock structures used to communicate SwitchInst code generation information.
Definition at line 342 of file SelectionDAGBuild.h.
| std::vector<std::pair<MachineInstr*, unsigned> > llvm::SelectionDAGLowering::PHINodesToUpdate |
Definition at line 344 of file SelectionDAGBuild.h.
Definition at line 348 of file SelectionDAGBuild.h.
FuncInfo - Information about the function as a whole.
Definition at line 352 of file SelectionDAGBuild.h.
Referenced by ExportFromCurrentBlock(), getValue(), isExportableFromCurrentBlock(), visitBitTestHeader(), and visitJumpTableHeader().
GFI - Garbage collection metadata for the function.
Definition at line 355 of file SelectionDAGBuild.h.
Referenced by init().
The documentation for this class was generated from the following files:
1.5.6