LLVM API Documentation

llvm::ARMTargetLowering Class Reference

#include <ARMISelLowering.h>

Inheritance diagram for llvm::ARMTargetLowering:

[legend]Collaboration diagram for llvm::ARMTargetLowering:

[legend]List of all members.


Public Member Functions
	ARMTargetLowering (TargetMachine &TM)
virtual SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG)
virtual SDNode *	ReplaceNodeResults (SDNode *N, SelectionDAG &DAG)
virtual SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const
virtual const char *	getTargetNodeName (unsigned Opcode) const
virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr MI, MachineBasicBlock MBB)
virtual bool	isLegalAddressingMode (const AddrMode &AM, const Type *Ty) const
virtual bool	getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG)
virtual bool	getPostIndexedAddressParts (SDNode N, SDNode Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG)
virtual void	computeMaskedBitsForTargetNode (const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const
ConstraintType	getConstraintType (const std::string &Constraint) const
std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const
std::vector< unsigned >	getRegClassForInlineAsmConstraint (const std::string &Constraint, MVT VT) const
virtual const ARMSubtarget *	getSubtarget ()

Constructor & Destructor Documentation

Member Function Documentation

void ARMTargetLowering::computeMaskedBitsForTargetNode ( const SDValue Op,

const APInt & Mask,

APInt & KnownZero,

APInt & KnownOne,

const SelectionDAG & DAG,

unsigned Depth

) const [virtual]

computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 1778 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::ComputeMaskedBits(), llvm::APInt::getBitWidth(), llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().

MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter ( MachineInstr * MI,

MachineBasicBlock * MBB

) [virtual]

Reimplemented from llvm::TargetLowering.
Definition at line 1452 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineFunction::DeleteMachineInstr(), llvm::TargetInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::TargetLowering::getTargetMachine(), llvm::MachineFunction::insert(), llvm::MachineBasicBlock::removeSuccessor(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_empty(), and llvm::MachineBasicBlock::succ_end().

ARMTargetLowering::ConstraintType ARMTargetLowering::getConstraintType ( const std::string & Constraint ) const [virtual]

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 1809 of file ARMISelLowering.cpp.
References llvm::TargetLowering::getConstraintType().

bool ARMTargetLowering::getPostIndexedAddressParts ( SDNode * N,

SDNode * Op,

SDValue & Base,

SDValue & Offset,

ISD::MemIndexedMode & AM,

SelectionDAG & DAG

) [virtual]

getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.
Reimplemented from llvm::TargetLowering.
Definition at line 1749 of file ARMISelLowering.cpp.
References llvm::LoadSDNode::getExtensionType(), getIndexedAddressParts(), llvm::MemSDNode::getMemoryVT(), and llvm::ARMSubtarget::isThumb().

bool ARMTargetLowering::getPreIndexedAddressParts ( SDNode * N,

SDValue & Base,

SDValue & Offset,

ISD::MemIndexedMode & AM,

SelectionDAG & DAG

) [virtual]

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.
Reimplemented from llvm::TargetLowering.
Definition at line 1716 of file ARMISelLowering.cpp.
References llvm::StoreSDNode::getBasePtr(), llvm::LoadSDNode::getBasePtr(), llvm::LoadSDNode::getExtensionType(), getIndexedAddressParts(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), and llvm::ARMSubtarget::isThumb().

std::vector< unsigned > ARMTargetLowering::getRegClassForInlineAsmConstraint ( const std::string & Constraint,

MVT VT

) const [virtual]

getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), return a list of registers that can be used to satisfy the constraint. This should only be used for C_RegisterClass constraints.
Reimplemented from llvm::TargetLowering.
Definition at line 1843 of file ARMISelLowering.cpp.

std::pair< unsigned, const TargetRegisterClass * > ARMTargetLowering::getRegForInlineAsmConstraint ( const std::string & Constraint,

MVT VT

) const [virtual]

getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register.
Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.
This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer..
Reimplemented from llvm::TargetLowering.
Definition at line 1821 of file ARMISelLowering.cpp.
References llvm::TargetLowering::getRegForInlineAsmConstraint().

virtual const ARMSubtarget* llvm::ARMTargetLowering::getSubtarget ( ) [inline, virtual]

Reimplemented from llvm::TargetLowering.
Definition at line 122 of file ARMISelLowering.h.

const char * ARMTargetLowering::getTargetNodeName ( unsigned Opcode ) const [virtual]

getTargetNodeName() - This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 273 of file ARMISelLowering.cpp.

bool ARMTargetLowering::isLegalAddressingMode ( const AddrMode & AM,

const Type * Ty

) const [virtual]

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Reimplemented from llvm::TargetLowering.
Definition at line 1599 of file ARMISelLowering.cpp.
References llvm::MVT::getSimpleVT(), llvm::TargetLowering::getValueType(), isLegalAddressImmediate(), llvm::isPowerOf2_32(), and llvm::ARMSubtarget::isThumb().

SDValue ARMTargetLowering::LowerOperation ( SDValue Op,

SelectionDAG & DAG

) [virtual]

LowerOperation - This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.
Reimplemented from llvm::TargetLowering.
Definition at line 1400 of file ARMISelLowering.cpp.
References ExpandBIT_CONVERT(), ExpandSRx(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::ARMSubtarget::isTargetDarwin(), LowerBR_CC(), LowerCALL(), LowerConstantPool(), LowerFCOPYSIGN(), LowerFORMAL_ARGUMENTS(), LowerFP_TO_INT(), LowerINT_TO_FP(), LowerINTRINSIC_WO_CHAIN(), LowerRET(), LowerSELECT_CC(), and LowerVASTART().

SDValue ARMTargetLowering::PerformDAGCombine ( SDNode * N,

DAGCombinerInfo & DCI

) const [virtual]

PerformDAGCombine - This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::TargetLowering.
Definition at line 1528 of file ARMISelLowering.cpp.
References llvm::SDNode::getOpcode(), and PerformFMRRDCombine().

SDNode * ARMTargetLowering::ReplaceNodeResults ( SDNode * N,

SelectionDAG & DAG

) [virtual]

ReplaceNodeResults - Provide custom lowering hooks for nodes with illegal result types.
Reimplemented from llvm::TargetLowering.
Definition at line 1437 of file ARMISelLowering.cpp.
References ExpandBIT_CONVERT(), ExpandSRx(), and llvm::SDNode::getOpcode().

The documentation for this class was generated from the following files:

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llvm::ARMTargetLowering Class Reference

Public Member Functions

Constructor & Destructor Documentation

Member Function Documentation