llvm::ARMTargetLowering Member List

This is the complete list of members for llvm::ARMTargetLowering, including all inherited members.

addLegalFPImmediate(const APFloat &Imm)	llvm::TargetLowering	[inline, protected]
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)	llvm::TargetLowering	[inline, protected]
addRegisterClass(MVT VT, TargetRegisterClass *RC)	llvm::TargetLowering	[inline, protected]
allowsUnalignedMemoryAccesses() const	llvm::TargetLowering	[inline]
allowUnalignedMemoryAccesses	llvm::TargetLowering	[protected]
ArgListTy typedef	llvm::TargetLowering
ARMTargetLowering(TargetMachine &TM)	llvm::ARMTargetLowering	[explicit]
BooleanContent enum name	llvm::TargetLowering
BuildSDIV(SDNode *N, SelectionDAG &DAG, std::vector< SDNode * > *Created) const	llvm::TargetLowering
BuildUDIV(SDNode *N, SelectionDAG &DAG, std::vector< SDNode * > *Created) const	llvm::TargetLowering
C_Memory enum value	llvm::TargetLowering
C_Other enum value	llvm::TargetLowering
C_Register enum value	llvm::TargetLowering
C_RegisterClass enum value	llvm::TargetLowering
C_Unknown enum value	llvm::TargetLowering
CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret)	llvm::TargetLowering	[inline, static]
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, bool hasMemory, SelectionDAG *DAG=0) const	llvm::TargetLowering	[virtual]
computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const	llvm::ARMTargetLowering	[virtual]
ComputeNumSignBitsForTargetNode(SDValue Op, unsigned Depth=0) const	llvm::TargetLowering	[virtual]
computeRegisterProperties()	llvm::TargetLowering	[protected]
ConstraintType enum name	llvm::TargetLowering
createFastISel(MachineFunction &, MachineModuleInfo *, DenseMap< const Value *, unsigned > &, DenseMap< const BasicBlock *, MachineBasicBlock * > &, DenseMap< const AllocaInst *, int > &, SmallSet< Instruction *, 8 > &CatchInfoLost)	llvm::TargetLowering	[inline, virtual]
Custom enum value	llvm::TargetLowering
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB)	llvm::ARMTargetLowering	[virtual]
EmitTargetCodeForMemmove(SelectionDAG &DAG, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, const Value *DstSV, uint64_t DstOff, const Value *SrcSV, uint64_t SrcOff)	llvm::TargetLowering	[inline, virtual]
EmitTargetCodeForMemset(SelectionDAG &DAG, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, const Value *DstSV, uint64_t DstOff)	llvm::TargetLowering	[inline, virtual]
Expand enum value	llvm::TargetLowering
Extend enum value	llvm::TargetLowering
getBooleanContents() const	llvm::TargetLowering	[inline]
getByValTypeAlignment(const Type *Ty) const	llvm::TargetLowering	[virtual]
getCmpLibcallCC(RTLIB::Libcall Call) const	llvm::TargetLowering	[inline]
getCondCodeAction(ISD::CondCode CC, MVT VT) const	llvm::TargetLowering	[inline]
getConstraintType(const std::string &Constraint) const	llvm::ARMTargetLowering	[virtual]
getConvertAction(MVT FromVT, MVT ToVT) const	llvm::TargetLowering	[inline]
getExceptionAddressRegister() const	llvm::TargetLowering	[inline]
getExceptionSelectorRegister() const	llvm::TargetLowering	[inline]
getIfCvtBlockSizeLimit() const	llvm::TargetLowering	[inline]
getIfCvtDupBlockSizeLimit() const	llvm::TargetLowering	[inline]
getIndexedLoadAction(unsigned IdxMode, MVT VT) const	llvm::TargetLowering	[inline]
getIndexedStoreAction(unsigned IdxMode, MVT VT) const	llvm::TargetLowering	[inline]
getJumpBufAlignment() const	llvm::TargetLowering	[inline]
getJumpBufSize() const	llvm::TargetLowering	[inline]
getLibcallName(RTLIB::Libcall Call) const	llvm::TargetLowering	[inline]
getLoadExtAction(unsigned LType, MVT VT) const	llvm::TargetLowering	[inline]
getMaxStoresPerMemcpy() const	llvm::TargetLowering	[inline]
getMaxStoresPerMemmove() const	llvm::TargetLowering	[inline]
getMaxStoresPerMemset() const	llvm::TargetLowering	[inline]
getNumRegisters(MVT VT) const	llvm::TargetLowering	[inline]
getOperationAction(unsigned Op, MVT VT) const	llvm::TargetLowering	[inline]
getOptimalMemOpType(uint64_t Size, unsigned Align, bool isSrcConst, bool isSrcStr) const	llvm::TargetLowering	[inline, virtual]
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const	llvm::TargetLowering	[virtual]
getPointerTy() const	llvm::TargetLowering	[inline]
GetPossiblePreceedingTailCall(SDValue Chain, unsigned TailCallNodeOpCode)	llvm::TargetLowering	[inline, static]
getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG)	llvm::ARMTargetLowering	[virtual]
getPrefLoopAlignment() const	llvm::TargetLowering	[inline]
getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG)	llvm::ARMTargetLowering	[virtual]
getRegClassFor(MVT VT) const	llvm::TargetLowering	[inline]
getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT VT) const	llvm::ARMTargetLowering	[virtual]
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const	llvm::ARMTargetLowering	[virtual]
getRegisterType(MVT VT) const	llvm::TargetLowering	[inline]
getSchedulingPreference() const	llvm::TargetLowering	[inline]
getSetCCResultType(MVT VT) const	llvm::TargetLowering	[virtual]
getShiftAmountFlavor() const	llvm::TargetLowering	[inline]
getShiftAmountTy() const	llvm::TargetLowering	[inline]
getStackPointerRegisterToSaveRestore() const	llvm::TargetLowering	[inline]
getSubtarget()	llvm::ARMTargetLowering	[inline, virtual]
getTargetData() const	llvm::TargetLowering	[inline]
getTargetMachine() const	llvm::TargetLowering	[inline]
getTargetNodeName(unsigned Opcode) const	llvm::ARMTargetLowering	[virtual]
getTgtMemIntrinsic(IntrinsicInfo &Info, CallInst &I, unsigned Intrinsic)	llvm::TargetLowering	[inline, virtual]
getTruncStoreAction(MVT ValVT, MVT MemVT) const	llvm::TargetLowering	[inline]
getTypeAction(MVT VT) const	llvm::TargetLowering	[inline]
getTypeToExpandTo(MVT VT) const	llvm::TargetLowering	[inline]
getTypeToPromoteTo(unsigned Op, MVT VT) const	llvm::TargetLowering	[inline]
getTypeToTransformTo(MVT VT) const	llvm::TargetLowering	[inline]
getValueType(const Type *Ty, bool AllowUnknown=false) const	llvm::TargetLowering	[inline]
getValueTypeActions() const	llvm::TargetLowering	[inline]
getVectorTypeBreakdown(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const	llvm::TargetLowering
getWidenVectorType(MVT VT)	llvm::TargetLowering	[virtual]
hasTargetDAGCombine(ISD::NodeType NT) const	llvm::TargetLowering	[inline]
IntrinisicInfo typedef	llvm::TargetLowering
isBigEndian() const	llvm::TargetLowering	[inline]
isCondCodeLegal(ISD::CondCode CC, MVT VT) const	llvm::TargetLowering	[inline]
isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist, const MachineFrameInfo *MFI) const	llvm::TargetLowering
isConvertLegal(MVT FromVT, MVT ToVT) const	llvm::TargetLowering	[inline]
IsEligibleForTailCallOptimization(CallSDNode *Call, SDValue Ret, SelectionDAG &DAG) const	llvm::TargetLowering	[inline, virtual]
isGAPlusOffset(SDNode *N, GlobalValue *&GA, int64_t &Offset) const	llvm::TargetLowering	[virtual]
isIndexedLoadLegal(unsigned IdxMode, MVT VT) const	llvm::TargetLowering	[inline]
isIndexedStoreLegal(unsigned IdxMode, MVT VT) const	llvm::TargetLowering	[inline]
isIntDivCheap() const	llvm::TargetLowering	[inline]
isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const	llvm::ARMTargetLowering	[virtual]
isLittleEndian() const	llvm::TargetLowering	[inline]
isLoadExtLegal(unsigned LType, MVT VT) const	llvm::TargetLowering	[inline]
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const	llvm::TargetLowering	[virtual]
isOperationLegal(unsigned Op, MVT VT) const	llvm::TargetLowering	[inline]
isPow2DivCheap() const	llvm::TargetLowering	[inline]
isSelectExpensive() const	llvm::TargetLowering	[inline]
isShuffleMaskLegal(SDValue Mask, MVT VT) const	llvm::TargetLowering	[inline, virtual]
isTruncateFree(const Type *Ty1, const Type *Ty2) const	llvm::TargetLowering	[inline, virtual]
isTruncateFree(MVT VT1, MVT VT2) const	llvm::TargetLowering	[inline, virtual]
isTruncStoreLegal(MVT ValVT, MVT MemVT) const	llvm::TargetLowering	[inline]
isTypeLegal(MVT VT) const	llvm::TargetLowering	[inline]
isVectorClearMaskLegal(const std::vector< SDValue > &BVOps, MVT EVT, SelectionDAG &DAG) const	llvm::TargetLowering	[inline, virtual]
Legal enum value	llvm::TargetLowering
legal_fpimm_begin() const	llvm::TargetLowering	[inline]
legal_fpimm_end() const	llvm::TargetLowering	[inline]
legal_fpimm_iterator typedef	llvm::TargetLowering
LegalizeAction enum name	llvm::TargetLowering
LowerArguments(Function &F, SelectionDAG &DAG, SmallVectorImpl< SDValue > &ArgValues)	llvm::TargetLowering	[virtual]
LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, bool hasMemory, std::vector< SDValue > &Ops, SelectionDAG &DAG) const	llvm::TargetLowering	[virtual]
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg, unsigned CallingConv, bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG)	llvm::TargetLowering	[virtual]
LowerOperation(SDValue Op, SelectionDAG &DAG)	llvm::ARMTargetLowering	[virtual]
LowerXConstraint(MVT ConstraintVT) const	llvm::TargetLowering	[virtual]
Mask enum value	llvm::TargetLowering
maxStoresPerMemcpy	llvm::TargetLowering	[protected]
maxStoresPerMemmove	llvm::TargetLowering	[protected]
maxStoresPerMemset	llvm::TargetLowering	[protected]
OutOfRangeShiftAmount enum name	llvm::TargetLowering
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const	llvm::ARMTargetLowering	[virtual]
Promote enum value	llvm::TargetLowering
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)	llvm::ARMTargetLowering	[virtual]
SchedPreference enum name	llvm::TargetLowering
SchedulingForLatency enum value	llvm::TargetLowering
SchedulingForRegPressure enum value	llvm::TargetLowering
setBooleanContents(BooleanContent Ty)	llvm::TargetLowering	[inline, protected]
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)	llvm::TargetLowering	[inline]
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)	llvm::TargetLowering	[inline, protected]
setConvertAction(MVT FromVT, MVT ToVT, LegalizeAction Action)	llvm::TargetLowering	[inline, protected]
setExceptionPointerRegister(unsigned R)	llvm::TargetLowering	[inline, protected]
setExceptionSelectorRegister(unsigned R)	llvm::TargetLowering	[inline, protected]
setIfCvtBlockSizeLimit(unsigned Limit)	llvm::TargetLowering	[inline, protected]
setIfCvtDupBlockSizeLimit(unsigned Limit)	llvm::TargetLowering	[inline, protected]
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)	llvm::TargetLowering	[inline, protected]
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)	llvm::TargetLowering	[inline, protected]
setIntDivIsCheap(bool isCheap=true)	llvm::TargetLowering	[inline, protected]
setJumpBufAlignment(unsigned Align)	llvm::TargetLowering	[inline, protected]
setJumpBufSize(unsigned Size)	llvm::TargetLowering	[inline, protected]
setLibcallName(RTLIB::Libcall Call, const char *Name)	llvm::TargetLowering	[inline]
setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)	llvm::TargetLowering	[inline, protected]
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)	llvm::TargetLowering	[inline, protected]
setPow2DivIsCheap(bool isCheap=true)	llvm::TargetLowering	[inline, protected]
setPrefLoopAlignment(unsigned Align)	llvm::TargetLowering	[inline, protected]
setSchedulingPreference(SchedPreference Pref)	llvm::TargetLowering	[inline, protected]
setSelectIsExpensive()	llvm::TargetLowering	[inline, protected]
setShiftAmountFlavor(OutOfRangeShiftAmount OORSA)	llvm::TargetLowering	[inline, protected]
setShiftAmountType(MVT VT)	llvm::TargetLowering	[inline, protected]
setStackPointerRegisterToSaveRestore(unsigned R)	llvm::TargetLowering	[inline, protected]
setTargetDAGCombine(ISD::NodeType NT)	llvm::TargetLowering	[inline, protected]
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)	llvm::TargetLowering	[inline, protected]
setUsesGlobalOffsetTable(bool V)	llvm::TargetLowering	[inline, protected]
setUseUnderscoreLongJmp(bool Val)	llvm::TargetLowering	[inline, protected]
setUseUnderscoreSetJmp(bool Val)	llvm::TargetLowering	[inline, protected]
ShouldShrinkFPConstant(MVT VT) const	llvm::TargetLowering	[inline, virtual]
SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const	llvm::TargetLowering
SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI) const	llvm::TargetLowering
TargetLowering(TargetMachine &TM)	llvm::TargetLowering	[explicit]
Undefined enum value	llvm::TargetLowering
UndefinedBooleanContent enum value	llvm::TargetLowering
usesGlobalOffsetTable() const	llvm::TargetLowering	[inline]
usesUnderscoreLongJmp() const	llvm::TargetLowering	[inline]
usesUnderscoreSetJmp() const	llvm::TargetLowering	[inline]
ZeroOrNegativeOneBooleanContent enum value	llvm::TargetLowering
ZeroOrOneBooleanContent enum value	llvm::TargetLowering
~TargetLowering()	llvm::TargetLowering	[virtual]