LLVM API Documentation

Main Page | Namespace List | Class Hierarchy | Alphabetical List | Class List | Directories | File List | Namespace Members | Class Members | File Members | Related Pages

llvm::ARMInstrInfo Class Reference

#include <ARMInstrInfo.h>

Inheritance diagram for llvm::ARMInstrInfo:

Inheritance graph
[legend]
Collaboration diagram for llvm::ARMInstrInfo:

Collaboration graph
[legend]
List of all members.

Public Member Functions

 ARMInstrInfo (const ARMSubtarget &STI)
virtual const ARMRegisterInfo & getRegisterInfo () const
virtual const TargetRegisterClass * getPointerRegClass () const
virtual bool isMoveInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const
virtual unsigned isLoadFromStackSlot (MachineInstr *MI, int &FrameIndex) const
virtual unsigned isStoreToStackSlot (MachineInstr *MI, int &FrameIndex) const
void reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const
virtual MachineInstr * convertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const
virtual bool AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond) const
virtual unsigned RemoveBranch (MachineBasicBlock &MBB) const
virtual unsigned InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond) const
virtual bool copyRegToReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const
 copyRegToReg - Add a copy between a pair of registers
virtual void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC) const
virtual void storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
virtual void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC) const
virtual void loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
virtual bool spillCalleeSavedRegisters (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI) const
virtual bool restoreCalleeSavedRegisters (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI) const
virtual MachineInstr * foldMemoryOperand (MachineFunction &MF, MachineInstr *MI, SmallVectorImpl< unsigned > &Ops, int FrameIndex) const
virtual MachineInstr * foldMemoryOperand (MachineFunction &MF, MachineInstr *MI, SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const
virtual bool canFoldMemoryOperand (MachineInstr *MI, SmallVectorImpl< unsigned > &Ops) const
virtual bool BlockHasNoFallThrough (MachineBasicBlock &MBB) const
virtual bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const
virtual bool isPredicated (const MachineInstr *MI) const
virtual bool PredicateInstruction (MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const
virtual bool SubsumesPredicate (const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const
virtual bool DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const
virtual unsigned GetInstSizeInBytes (const MachineInstr *MI) const

Constructor & Destructor Documentation

ARMInstrInfo::ARMInstrInfo (  const ARMSubtarget &  STI  )  [explicit]
 

Definition at line 41 of file ARMInstrInfo.cpp.

References llvm::array_lengthof().

Member Function Documentation

bool ARMInstrInfo::AnalyzeBranch (  MachineBasicBlock &  MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond
)  const [virtual]
 

AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with an conditional branch and it falls through to an successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with an conditional branch and an unconditional block, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that RemoveBranch and InsertBranch must be implemented to support cases where this method returns success.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 334 of file ARMInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), and llvm::SmallVectorImpl< T >::push_back().

bool ARMInstrInfo::BlockHasNoFallThrough (  MachineBasicBlock &  MBB  )  const [virtual]
 

BlockHasNoFallThrough - Return true if the specified block does not fall-through into its successor block. This is primarily used when a branch is unanalyzable. It is useful for things like unconditional indirect branches (jump tables).

Reimplemented from llvm::TargetInstrInfo.

Definition at line 783 of file ARMInstrInfo.cpp.

References llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::empty(), and llvm::MachineInstr::getOpcode().

bool ARMInstrInfo::canFoldMemoryOperand (  MachineInstr *  MI,
SmallVectorImpl< unsigned > &  Ops
)  const [virtual]
 

canFoldMemoryOperand - Returns true if the specified load / store is folding is possible.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 750 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::ARMRegisterInfo::isLowRegister(), and llvm::SmallVectorImpl< T >::size().

MachineInstr * ARMInstrInfo::convertToThreeAddress (  MachineFunction::iterator &  MFI,
MachineBasicBlock::iterator &  MBBI,
LiveVariables *  LV
)  const [virtual]
 

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into one or more true three-address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the last new instruction.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 192 of file ARMInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::BuildMI(), llvm::TargetInstrInfo::get(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isRegister(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::LiveVariables::VarInfo::Kills, llvm::TargetInstrDesc::mayStore(), llvm::MachineInstr::readsRegister(), Reg, llvm::LiveVariables::VarInfo::removeKill(), llvm::MachineOperand::setIsDead(), and llvm::TargetInstrDesc::TSFlags.

bool ARMInstrInfo::copyRegToReg (  MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
unsigned  DestReg,
unsigned  SrcReg,
const TargetRegisterClass *  DestRC,
const TargetRegisterClass *  SrcRC
)  const [virtual]
 

copyRegToReg - Add a copy between a pair of registers

Reimplemented from llvm::TargetInstrInfo.

Definition at line 462 of file ARMInstrInfo.cpp.

References AddDefaultCC(), AddDefaultPred(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), and llvm::ARMFunctionInfo::isThumbFunction().

bool ARMInstrInfo::DefinesPredicate (  MachineInstr *  MI,
std::vector< MachineOperand > &  Pred
)  const [virtual]
 

DefinesPredicate - If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 862 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::TargetInstrDesc::getImplicitDefs(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::TargetInstrDesc::hasOptionalDef(), and llvm::MachineOperand::isRegister().

virtual MachineInstr* llvm::ARMInstrInfo::foldMemoryOperand (  MachineFunction &  MF,
MachineInstr *  MI,
SmallVectorImpl< unsigned > &  Ops,
MachineInstr *  LoadMI
)  const [inline, virtual]
 

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 202 of file ARMInstrInfo.h.

MachineInstr * ARMInstrInfo::foldMemoryOperand (  MachineFunction &  MF,
MachineInstr *  MI,
SmallVectorImpl< unsigned > &  Ops,
int  FI
)  const [virtual]
 

foldMemoryOperand - Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The client is responsible for removing the old instruction and adding the new one in the instruction stream.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 664 of file ARMInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::get(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::ARMRegisterInfo::isLowRegister(), and llvm::SmallVectorImpl< T >::size().

unsigned ARMInstrInfo::GetInstSizeInBytes (  const MachineInstr *  MI  )  const [virtual]
 

GetInstSize - Returns the size of the specified MachineInstr.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 891 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::TargetAsmInfo::getInlineAsmLength(), llvm::MachineFunction::getJumpTableInfo(), llvm::MachineJumpTableInfo::getJumpTables(), getNumJTEntries(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::getTargetAsmInfo(), llvm::MachineInstr::isLabel(), llvm::TargetInstrDesc::isPredicable(), and llvm::TargetInstrDesc::TSFlags.

const TargetRegisterClass * ARMInstrInfo::getPointerRegClass (   )  const [virtual]
 

getPointerRegClass - Return the register class to use to hold pointers. This is used for addressing modes.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 46 of file ARMInstrInfo.cpp.

virtual const ARMRegisterInfo& llvm::ARMInstrInfo::getRegisterInfo (   )  const [inline, virtual]
 

getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 137 of file ARMInstrInfo.h.

unsigned ARMInstrInfo::InsertBranch (  MachineBasicBlock &  MBB,
MachineBasicBlock *  TBB,
MachineBasicBlock *  FBB,
const SmallVectorImpl< MachineOperand > &  Cond
)  const [virtual]
 

InsertBranch - Insert a branch into the end of the specified MachineBasicBlock. This operands to this method are the same as those returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch returns success and when an unconditional branch (TBB is non-null, FBB is null, Cond is empty) needs to be inserted. It returns the number of instructions inserted.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 433 of file ARMInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SmallVectorImpl< T >::empty(), llvm::TargetInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::isThumbFunction(), and llvm::SmallVectorImpl< T >::size().

unsigned ARMInstrInfo::isLoadFromStackSlot (  MachineInstr *  MI,
int &  FrameIndex
)  const [virtual]
 

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 76 of file ARMInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFrameIndex(), llvm::MachineOperand::isImmediate(), and llvm::MachineOperand::isRegister().

bool ARMInstrInfo::isMoveInstr (  const MachineInstr &  MI,
unsigned &  SrcReg,
unsigned &  DstReg
)  const [virtual]
 

Return true if the instruction is a register to register move and leave the source and dest operands in the passed parameters.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 53 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::TargetInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isRegister().

bool ARMInstrInfo::isPredicated (  const MachineInstr *  MI  )  const [virtual]
 

isPredicated - Returns true if the instruction is already predicated.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 810 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), and llvm::MachineInstr::getOperand().

unsigned ARMInstrInfo::isStoreToStackSlot (  MachineInstr *  MI,
int &  FrameIndex
)  const [virtual]
 

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 110 of file ARMInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFrameIndex(), llvm::MachineOperand::isImmediate(), and llvm::MachineOperand::isRegister().

void ARMInstrInfo::loadRegFromAddr (  MachineFunction &  MF,
unsigned  DestReg,
SmallVectorImpl< MachineOperand > &  Addr,
const TargetRegisterClass *  RC,
SmallVectorImpl< MachineInstr * > &  NewMIs
)  const [virtual]
 

Reimplemented from llvm::TargetInstrInfo.

Definition at line 589 of file ARMInstrInfo.cpp.

References AddDefaultPred(), ARMInstrAddOperand(), llvm::BuildMI(), llvm::TargetInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().

void ARMInstrInfo::loadRegFromStackSlot (  MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass *  RC
)  const [virtual]
 

Reimplemented from llvm::TargetInstrInfo.

Definition at line 567 of file ARMInstrInfo.cpp.

References AddDefaultPred(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::TargetInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), and llvm::ARMFunctionInfo::isThumbFunction().

bool ARMInstrInfo::PredicateInstruction (  MachineInstr *  MI,
const SmallVectorImpl< MachineOperand > &  Pred
)  const [virtual]
 

PredicateInstruction - Convert the instruction into a predicated instruction. It returns true if the operation was successful.

Reimplemented from llvm::TargetInstrInfoImpl.

Definition at line 815 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::TargetInstrInfo::get(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().

void ARMInstrInfo::reMaterialize (  MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
const MachineInstr *  Orig
)  const [virtual]
 

reMaterialize - Re-issue the specified 'original' instruction at the specific location targeting a new destination register.

Reimplemented from llvm::TargetInstrInfoImpl.

Definition at line 144 of file ARMInstrInfo.cpp.

References llvm::MachineFunction::CloneMachineInstr(), llvm::ARMRegisterInfo::emitLoadConstPool(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), and llvm::MachineOperand::setReg().

unsigned ARMInstrInfo::RemoveBranch (  MachineBasicBlock &  MBB  )  const [virtual]
 

RemoveBranch - Remove the branching code at the end of the specific MBB. this is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 406 of file ARMInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), and llvm::ARMFunctionInfo::isThumbFunction().

bool ARMInstrInfo::restoreCalleeSavedRegisters (  MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
const std::vector< CalleeSavedInfo > &  CSI
)  const [virtual]
 

restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot(). Returns false otherwise.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 638 of file ARMInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), llvm::MachineFunction::CreateMachineInstr(), llvm::MachineBasicBlock::erase(), llvm::TargetInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::getVarArgsRegSaveSize(), llvm::MachineBasicBlock::insert(), llvm::ARMFunctionInfo::isThumbFunction(), Reg, and llvm::MachineInstr::setDesc().

bool ARMInstrInfo::ReverseBranchCondition (  SmallVectorImpl< MachineOperand > &  Cond  )  const [virtual]
 

ReverseBranchCondition - Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 804 of file ARMInstrInfo.cpp.

bool ARMInstrInfo::spillCalleeSavedRegisters (  MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
const std::vector< CalleeSavedInfo > &  CSI
)  const [virtual]
 

spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns true if it isn't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot(). Returns false otherwise.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 620 of file ARMInstrInfo.cpp.

References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::ARMFunctionInfo::isThumbFunction(), and Reg.

void ARMInstrInfo::storeRegToAddr (  MachineFunction &  MF,
unsigned  SrcReg,
bool  isKill,
SmallVectorImpl< MachineOperand > &  Addr,
const TargetRegisterClass *  RC,
SmallVectorImpl< MachineInstr * > &  NewMIs
)  const [virtual]
 

Reimplemented from llvm::TargetInstrInfo.

Definition at line 532 of file ARMInstrInfo.cpp.

References AddDefaultPred(), llvm::MachineInstrBuilder::addReg(), ARMInstrAddOperand(), llvm::BuildMI(), llvm::TargetInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().

void ARMInstrInfo::storeRegToStackSlot (  MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass *  RC
)  const [virtual]
 

Reimplemented from llvm::TargetInstrInfo.

Definition at line 507 of file ARMInstrInfo.cpp.

References AddDefaultPred(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), and llvm::ARMFunctionInfo::isThumbFunction().

bool ARMInstrInfo::SubsumesPredicate (  const SmallVectorImpl< MachineOperand > &  Pred1,
const SmallVectorImpl< MachineOperand > &  Pred2
)  const [virtual]
 

SubsumesPredicate - Returns true if the first specified predicate subsumes the second, e.g. GE subsumes GT.

Reimplemented from llvm::TargetInstrInfo.

Definition at line 836 of file ARMInstrInfo.cpp.

References llvm::SmallVectorImpl< T >::size().

The documentation for this class was generated from the following files:

Generated on Thu Aug 28 02:56:29 2008 for LLVM by Doxygen1.3.9.1
Copyright © 2003-2007 University of Illinois at Urbana-Champaign. All Rights Reserved.

This web site is hosted by the Computer Science Department at the University of Illinois at Urbana-Champaign.