X86InstrInfo.h File Reference

#include "llvm/Target/TargetInstrInfo.h"
#include "X86.h"
#include "X86RegisterInfo.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/Target/TargetRegisterInfo.h"

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Namespaces
namespace	llvm
namespace	llvm::X86
namespace	llvm::X86II
Classes
class	llvm::X86InstrInfo
Enumerations
enum	llvm::X86::CondCode {   llvm::X86::COND_A = 0, llvm::X86::COND_AE = 1, llvm::X86::COND_B = 2, llvm::X86::COND_BE = 3,   llvm::X86::COND_E = 4, llvm::X86::COND_G = 5, llvm::X86::COND_GE = 6, llvm::X86::COND_L = 7,   llvm::X86::COND_LE = 8, llvm::X86::COND_NE = 9, llvm::X86::COND_NO = 10, llvm::X86::COND_NP = 11,   llvm::X86::COND_NS = 12, llvm::X86::COND_O = 13, llvm::X86::COND_P = 14, llvm::X86::COND_S = 15,   llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP_OR_E, llvm::X86::COND_INVALID }
enum	{   llvm::X86II::Pseudo = 0, llvm::X86II::RawFrm = 1, llvm::X86II::AddRegFrm = 2, llvm::X86II::MRMDestReg = 3,   llvm::X86II::MRMDestMem = 4, llvm::X86II::MRMSrcReg = 5, llvm::X86II::MRMSrcMem = 6, llvm::X86II::MRM0r = 16,   llvm::X86II::MRM1r = 17, llvm::X86II::MRM2r = 18, llvm::X86II::MRM3r = 19, llvm::X86II::MRM4r = 20,   llvm::X86II::MRM5r = 21, llvm::X86II::MRM6r = 22, llvm::X86II::MRM7r = 23, llvm::X86II::MRM0m = 24,   llvm::X86II::MRM1m = 25, llvm::X86II::MRM2m = 26, llvm::X86II::MRM3m = 27, llvm::X86II::MRM4m = 28,   llvm::X86II::MRM5m = 29, llvm::X86II::MRM6m = 30, llvm::X86II::MRM7m = 31, llvm::X86II::MRMInitReg = 32,   llvm::X86II::FormMask = 63, llvm::X86II::OpSize = 1 << 6, llvm::X86II::AdSize = 1 << 7, llvm::X86II::Op0Shift = 8,   llvm::X86II::Op0Mask = 0xF << Op0Shift, llvm::X86II::TB = 1 << Op0Shift, llvm::X86II::REP = 2 << Op0Shift, llvm::X86II::D8 = 3 << Op0Shift,   llvm::X86II::D9 = 4 << Op0Shift, llvm::X86II::DA = 5 << Op0Shift, llvm::X86II::DB = 6 << Op0Shift, llvm::X86II::DC = 7 << Op0Shift,   llvm::X86II::DD = 8 << Op0Shift, llvm::X86II::DE = 9 << Op0Shift, llvm::X86II::DF = 10 << Op0Shift, llvm::X86II::XD = 11 << Op0Shift,   llvm::X86II::XS = 12 << Op0Shift, llvm::X86II::T8 = 13 << Op0Shift, llvm::X86II::TA = 14 << Op0Shift, llvm::X86II::REXShift = 12,   llvm::X86II::REX_W = 1 << REXShift, llvm::X86II::ImmShift = 13, llvm::X86II::ImmMask = 7 << ImmShift, llvm::X86II::Imm8 = 1 << ImmShift,   llvm::X86II::Imm16 = 2 << ImmShift, llvm::X86II::Imm32 = 3 << ImmShift, llvm::X86II::Imm64 = 4 << ImmShift, llvm::X86II::FPTypeShift = 16,   llvm::X86II::FPTypeMask = 7 << FPTypeShift, llvm::X86II::NotFP = 0 << FPTypeShift, llvm::X86II::ZeroArgFP = 1 << FPTypeShift, llvm::X86II::OneArgFP = 2 << FPTypeShift,   llvm::X86II::OneArgFPRW = 3 << FPTypeShift, llvm::X86II::TwoArgFP = 4 << FPTypeShift, llvm::X86II::CompareFP = 5 << FPTypeShift, llvm::X86II::CondMovFP = 6 << FPTypeShift,   llvm::X86II::SpecialFP = 7 << FPTypeShift, llvm::X86II::LOCKShift = 19, llvm::X86II::LOCK = 1 << LOCKShift, llvm::X86II::SegOvrShift = 20,   llvm::X86II::SegOvrMask = 3 << SegOvrShift, llvm::X86II::FS = 1 << SegOvrShift, llvm::X86II::GS = 2 << SegOvrShift, llvm::X86II::OpcodeShift = 24,   llvm::X86II::OpcodeMask = 0xFF << OpcodeShift }
Functions
unsigned	llvm::X86::GetCondBranchFromCond (CondCode CC)
CondCode	llvm::X86::GetOppositeBranchCondition (X86::CondCode CC)
static bool	llvm::isScale (const MachineOperand &MO)
static bool	llvm::isMem (const MachineInstr *MI, unsigned Op)