LLVM API Documentation

X86ISelLowering.cpp File Reference

#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86ISelLowering.h"
#include "X86MachineFunctionInfo.h"
#include "X86TargetMachine.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/GlobalVariable.h"
#include "llvm/Function.h"
#include "llvm/Intrinsics.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "X86GenCallingConv.inc"

Include dependency graph for X86ISelLowering.cpp:

Go to the source code of this file.

Functions

static SDValue getMOVLMask (unsigned NumElems, SelectionDAG &DAG)
static void getMaxByValAlign (const Type *Ty, unsigned &MaxAlign)
static unsigned AddLiveIn (MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
static bool CallIsStructReturn (CallSDNode *TheCall)
static bool ArgsAreStructReturn (SDValue Op)
static SDValue CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG)
static SDValue EmitTailCallStoreRetAddr (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, bool Is64Bit, int FPDiff)
static bool translateX86CC (ISD::CondCode SetCCOpcode, bool isFP, unsigned &X86CC, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
static bool hasFPCMov (unsigned X86CC)
static bool isUndefOrInRange (SDValue Op, unsigned Low, unsigned Hi)
static bool isUndefOrEqual (SDValue Op, unsigned Val)
static bool isSHUFPMask (SDOperandPtr Elems, unsigned NumElems)
static bool isCommutedSHUFP (SDOperandPtr Ops, unsigned NumOps)
static bool isCommutedSHUFP (SDNode *N)
static bool isUNPCKLMask (SDOperandPtr Elts, unsigned NumElts, bool V2IsSplat=false)
static bool isUNPCKHMask (SDOperandPtr Elts, unsigned NumElts, bool V2IsSplat=false)
static bool isMOVLMask (SDOperandPtr Elts, unsigned NumElts)
static bool isCommutedMOVL (SDOperandPtr Ops, unsigned NumOps, bool V2IsSplat=false, bool V2IsUndef=false)
static bool isCommutedMOVL (SDNode *N, bool V2IsSplat=false, bool V2IsUndef=false)
static bool isIdentityMask (SDNode *N, bool RHS=false)
static bool isSplatMask (SDNode *N)
static bool isPSHUFHW_PSHUFLWMask (SDNode *N)
static SDValue CommuteVectorShuffle (SDValue Op, SDValue &V1, SDValue &V2, SDValue &Mask, SelectionDAG &DAG)
static SDValue CommuteVectorShuffleMask (SDValue Mask, SelectionDAG &DAG)
static bool ShouldXformToMOVHLPS (SDNode *Mask)
static bool isScalarLoadToVector (SDNode *N, LoadSDNode **LD=NULL)
static bool ShouldXformToMOVLP (SDNode *V1, SDNode *V2, SDNode *Mask)
static bool isSplatVector (SDNode *N)
static bool isUndefShuffle (SDNode *N)
static bool isZeroNode (SDValue Elt)
static bool isZeroShuffle (SDNode *N)
static SDValue getZeroVector (MVT VT, bool HasSSE2, SelectionDAG &DAG)
static SDValue getOnesVector (MVT VT, SelectionDAG &DAG)
static SDValue NormalizeMask (SDValue Mask, SelectionDAG &DAG)
static SDValue getUnpacklMask (unsigned NumElems, SelectionDAG &DAG)
static SDValue getUnpackhMask (unsigned NumElems, SelectionDAG &DAG)
static SDValue getSwapEltZeroMask (unsigned NumElems, unsigned DestElt, SelectionDAG &DAG)
static SDValue PromoteSplat (SDValue Op, SelectionDAG &DAG, bool HasSSE2)
 PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
static bool isVectorLoad (SDValue Op)
static SDValue CanonicalizeMovddup (SDValue Op, SDValue V1, SDValue Mask, SelectionDAG &DAG, bool HasSSE3)
static SDValue getShuffleVectorZeroOrUndef (SDValue V2, unsigned Idx, bool isZero, bool HasSSE2, SelectionDAG &DAG)
static unsigned getNumOfConsecutiveZeros (SDValue Op, SDValue Mask, unsigned NumElems, bool Low, SelectionDAG &DAG)
static bool isVectorShift (SDValue Op, SDValue Mask, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt)
static SDValue LowerBuildVectorv16i8 (SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, TargetLowering &TLI)
static SDValue LowerBuildVectorv8i16 (SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, TargetLowering &TLI)
static SDValue getVShift (bool isLeft, MVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue LowerVECTOR_SHUFFLEv8i16 (SDValue V1, SDValue V2, SDValue PermMask, SelectionDAG &DAG, TargetLowering &TLI)
static SDValue RewriteAsNarrowerShuffle (SDValue V1, SDValue V2, MVT VT, SDValue PermMask, SelectionDAG &DAG, TargetLowering &TLI)
static SDValue getVZextMovL (MVT VT, MVT OpVT, SDValue SrcOp, SelectionDAG &DAG, const X86Subtarget *Subtarget)
static SDValue LowerVECTOR_SHUFFLE_4wide (SDValue V1, SDValue V2, SDValue PermMask, MVT VT, SelectionDAG &DAG)
static SDValue LowerToTLSGeneralDynamicModel32 (GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT)
static SDValue LowerToTLSGeneralDynamicModel64 (GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT)
static SDValue LowerToTLSExecModel (GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT)
static bool isBaseAlignmentOfN (unsigned N, SDNode *Base, const TargetLowering &TLI)
static bool EltsFromConsecutiveLoads (SDNode *N, SDValue PermMask, unsigned NumElems, MVT EVT, SDNode *&Base, SelectionDAG &DAG, MachineFrameInfo *MFI, const TargetLowering &TLI)
static SDValue PerformShuffleCombine (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue PerformBuildVectorCombine (SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI)
 PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
static SDValue PerformSELECTCombine (SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
 PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
static SDValue PerformSTORECombine (SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
 PerformSTORECombine - Do target-specific dag combines on STORE nodes.
static SDValue PerformFORCombine (SDNode *N, SelectionDAG &DAG)
static SDValue PerformFANDCombine (SDNode *N, SelectionDAG &DAG)
 PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.

Function Documentation

static unsigned AddLiveIn ( MachineFunction &  MF,
unsigned  PReg,
const TargetRegisterClass *  RC 
) [static]

AddLiveIn - This helper function adds the specified physical register to the MachineFunction as a live in value. It also creates a corresponding virtual register for it.

Definition at line 1043 of file X86ISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), llvm::TargetRegisterClass::contains(), llvm::MachineRegisterInfo::createVirtualRegister(), and llvm::MachineFunction::getRegInfo().

static bool ArgsAreStructReturn ( SDValue  Op  )  [static]

ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct return semantics.

Definition at line 1063 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), and llvm::SDValue::getOperand().

static bool CallIsStructReturn ( CallSDNode *  TheCall  )  [static]

CallIsStructReturn - Determines whether a CALL node uses struct return semantics.

Definition at line 1053 of file X86ISelLowering.cpp.

References llvm::CallSDNode::getArgFlags(), llvm::CallSDNode::getNumArgs(), and llvm::ISD::ArgFlagsTy::isSRet().

static SDValue CanonicalizeMovddup ( SDValue  Op,
SDValue  V1,
SDValue  Mask,
SelectionDAG &  DAG,
bool  HasSSE3 
) [static]

CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.

Definition at line 2987 of file X86ISelLowering.cpp.

References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, isVectorLoad(), llvm::ISD::UNDEF, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::ISD::VECTOR_SHUFFLE.

static SDValue CommuteVectorShuffle ( SDValue  Op,
SDValue &  V1,
SDValue &  V2,
SDValue &  Mask,
SelectionDAG &  DAG 
) [static]

CommuteVectorShuffle - Swap vector_shuffle operands as well as values in ther permute mask.

Definition at line 2640 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), std::swap(), llvm::ISD::UNDEF, and llvm::ISD::VECTOR_SHUFFLE.

static SDValue CommuteVectorShuffleMask ( SDValue  Mask,
SelectionDAG &  DAG 
) [static]

CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming the two vector operands have swapped position.

Definition at line 2671 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::ISD::UNDEF.

Referenced by LowerVECTOR_SHUFFLE_4wide(), and LowerVECTOR_SHUFFLEv8i16().

static SDValue CreateCopyOfByValArgument ( SDValue  Src,
SDValue  Dst,
SDValue  Chain,
ISD::ArgFlagsTy  Flags,
SelectionDAG &  DAG 
) [static]

CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" with size and alignment information specified by the specific parameter attribute. The copy will be passed as a byval function parameter.

Definition at line 1145 of file X86ISelLowering.cpp.

References llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemcpy(), and llvm::MVT::i32.

static bool EltsFromConsecutiveLoads ( SDNode *  N,
SDValue  PermMask,
unsigned  NumElems,
MVT  EVT,
SDNode *&  Base,
SelectionDAG &  DAG,
MachineFrameInfo *  MFI,
const TargetLowering &  TLI 
) [static]

Definition at line 7028 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getShuffleScalarElt(), llvm::MVT::getSizeInBits(), llvm::TargetLowering::isConsecutiveLoad(), llvm::ISD::isNON_EXTLoad(), and llvm::ISD::UNDEF.

Referenced by PerformShuffleCombine().

static SDValue EmitTailCallStoreRetAddr ( SelectionDAG &  DAG,
MachineFunction &  MF,
SDValue  Chain,
SDValue  RetAddrFrIdx,
bool  Is64Bit,
int  FPDiff 
) [static]

EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call optimization is performed and it is required (FPDiff!=0).

Definition at line 1450 of file X86ISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::PseudoSourceValue::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getStore(), llvm::MVT::i32, and llvm::MVT::i64.

static void getMaxByValAlign ( const Type *  Ty,
unsigned &  MaxAlign 
) [static]

getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.

Definition at line 793 of file X86ISelLowering.cpp.

Referenced by llvm::X86TargetLowering::getByValTypeAlignment().

static SDValue getMOVLMask ( unsigned  NumElems,
SelectionDAG &  DAG 
) [static]

getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd operation of specified width.

Definition at line 2895 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().

static unsigned getNumOfConsecutiveZeros ( SDValue  Op,
SDValue  Mask,
unsigned  NumElems,
bool  Low,
SelectionDAG &  DAG 
) [static]

getNumOfConsecutiveZeros - Return the number of elements in a result of a shuffle that is zero.

Definition at line 3040 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getShuffleScalarElt(), Idx, Index, isZeroNode(), and llvm::ISD::UNDEF.

Referenced by isVectorShift().

static SDValue getOnesVector ( MVT  VT,
SelectionDAG &  DAG 
) [static]

getOnesVector - Returns a vector of specified type with all bits set.

Definition at line 2852 of file X86ISelLowering.cpp.

References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::isVector(), llvm::MVT::v2i32, and llvm::MVT::v4i32.

static SDValue getShuffleVectorZeroOrUndef ( SDValue  V2,
unsigned  Idx,
bool  isZero,
bool  HasSSE2,
SelectionDAG &  DAG 
) [static]

getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified vector of zero or undef vector. This produces a shuffle where the low element of V2 is swizzled into the zero/undef vector, landing at element Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).

Definition at line 3017 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), getZeroVector(), llvm::SmallVectorImpl< T >::push_back(), llvm::SmallVectorImpl< T >::size(), llvm::ISD::UNDEF, V1, and llvm::ISD::VECTOR_SHUFFLE.

static SDValue getSwapEltZeroMask ( unsigned  NumElems,
unsigned  DestElt,
SelectionDAG &  DAG 
) [static]

getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps element #0 of a vector with the specified index, leaving the rest of the elements in place.

Definition at line 2936 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().

static SDValue getUnpackhMask ( unsigned  NumElems,
SelectionDAG &  DAG 
) [static]

getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation of specified width.

Definition at line 2921 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().

static SDValue getUnpacklMask ( unsigned  NumElems,
SelectionDAG &  DAG 
) [static]

getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation of specified width.

Definition at line 2908 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::SmallVectorImpl< T >::push_back(), and llvm::SmallVectorImpl< T >::size().

Referenced by PromoteSplat().

static SDValue getVShift ( bool  isLeft,
MVT  VT,
SDValue  SrcOp,
unsigned  NumBits,
SelectionDAG &  DAG,
const TargetLowering &  TLI 
) [static]

getVShift - Return a vector logical shift node.

Definition at line 3175 of file X86ISelLowering.cpp.

References llvm::ISD::BIT_CONVERT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getShiftAmountTy(), llvm::MVT::getSizeInBits(), llvm::MVT::v1i64, llvm::MVT::v2i64, llvm::X86ISD::VSHL, and llvm::X86ISD::VSRL.

static SDValue getVZextMovL ( MVT  VT,
MVT  OpVT,
SDValue  SrcOp,
SelectionDAG &  DAG,
const X86Subtarget *  Subtarget 
) [static]

getVZextMovL - Return a zero-extending vector move low node.

Definition at line 3742 of file X86ISelLowering.cpp.

References llvm::ISD::BIT_CONVERT, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), isScalarLoadToVector(), llvm::ISD::SCALAR_TO_VECTOR, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::X86ISD::VZEXT_MOVL.

static SDValue getZeroVector ( MVT  VT,
bool  HasSSE2,
SelectionDAG &  DAG 
) [static]

getZeroVector - Returns a vector of specified type with all zero elements.

Definition at line 2831 of file X86ISelLowering.cpp.

References llvm::ISD::BIT_CONVERT, llvm::ISD::BUILD_VECTOR, llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetConstantFP(), llvm::MVT::i32, llvm::MVT::isVector(), llvm::MVT::v2i32, llvm::MVT::v4f32, and llvm::MVT::v4i32.

Referenced by getShuffleVectorZeroOrUndef(), LowerBuildVectorv16i8(), LowerBuildVectorv8i16(), and PromoteSplat().

static bool hasFPCMov ( unsigned  X86CC  )  [static]

hasFPCMov - is there a floating point cmov for the specific X86 condition code. Current x86 isa includes the following FP cmov instructions: fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.

Definition at line 2027 of file X86ISelLowering.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::X86::COND_NP, and llvm::X86::COND_P.

static bool isBaseAlignmentOfN ( unsigned  N,
SDNode *  Base,
const TargetLowering &  TLI 
) [static]

Definition at line 7018 of file X86ISelLowering.cpp.

References llvm::GlobalValue::getAlignment(), and llvm::TargetLowering::isGAPlusOffset().

Referenced by PerformShuffleCombine().

static bool isCommutedMOVL ( SDNode *  N,
bool  V2IsSplat = false,
bool  V2IsUndef = false 
) [static]

Definition at line 2399 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), isCommutedMOVL(), and llvm::SDNode::op_begin().

static bool isCommutedMOVL ( SDOperandPtr  Ops,
unsigned  NumOps,
bool  V2IsSplat = false,
bool  V2IsUndef = false 
) [static]

isCommutedMOVL - Returns true if the shuffle mask is except the reverse of what x86 movss want. X86 movs requires the lowest element to be lowest element of vector 2 and the other elements to come from vector 1 in order.

Definition at line 2379 of file X86ISelLowering.cpp.

References isUndefOrEqual(), and isUndefOrInRange().

Referenced by isCommutedMOVL(), and llvm::X86TargetLowering::isVectorClearMaskLegal().

static bool isCommutedSHUFP ( SDNode *  N  )  [static]

Definition at line 2170 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), isCommutedSHUFP(), and llvm::SDNode::op_begin().

static bool isCommutedSHUFP ( SDOperandPtr  Ops,
unsigned  NumOps 
) [static]

isCommutedSHUFP - Returns true if the shuffle mask is exactly the reverse of what x86 shuffles want. x86 shuffles requires the lower half elements to come from vector 1 (which would equal the dest.) and the upper half to come from vector 2.

Definition at line 2157 of file X86ISelLowering.cpp.

References isUndefOrInRange().

Referenced by isCommutedSHUFP(), and llvm::X86TargetLowering::isVectorClearMaskLegal().

static bool isIdentityMask ( SDNode *  N,
bool  RHS = false 
) [static]

isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand specifies a identity operation on the LHS or RHS.

Definition at line 2470 of file X86ISelLowering.cpp.

References llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), isUndefOrEqual(), and RHS.

Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().

static bool isMOVLMask ( SDOperandPtr  Elts,
unsigned  NumElts 
) [static]

isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSS, MOVSD, and MOVD, i.e. setting the lowest element.

Definition at line 2356 of file X86ISelLowering.cpp.

References isUndefOrEqual().

Referenced by llvm::X86::isMOVLMask(), and llvm::X86TargetLowering::isVectorClearMaskLegal().

static bool isPSHUFHW_PSHUFLWMask ( SDNode *  N  )  [static]

isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand specifies a 8 element shuffle that can be broken into a pair of PSHUFHW and PSHUFLW.

Definition at line 2609 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().

static bool isScalarLoadToVector ( SDNode *  N,
LoadSDNode **  LD = NULL 
) [static]

isScalarLoadToVector - Returns true if the node is a scalar load that is promoted to a vector. It also returns the LoadSDNode by reference if required.

Definition at line 2713 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isNON_EXTLoad(), and llvm::ISD::SCALAR_TO_VECTOR.

Referenced by getVZextMovL(), and ShouldXformToMOVLP().

static bool isSHUFPMask ( SDOperandPtr  Elems,
unsigned  NumElems 
) [static]

isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to SHUFP*.

Definition at line 2134 of file X86ISelLowering.cpp.

References isUndefOrInRange().

Referenced by llvm::X86::isSHUFPMask(), and llvm::X86TargetLowering::isVectorClearMaskLegal().

static bool isSplatMask ( SDNode *  N  )  [static]

isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element.

Definition at line 2480 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::UNDEF.

Referenced by llvm::X86TargetLowering::isShuffleMaskLegal(), and llvm::X86::isSplatMask().

static bool isSplatVector ( SDNode *  N  )  [static]

isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are all the same.

Definition at line 2751 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().

static bool isUndefOrEqual ( SDValue  Op,
unsigned  Val 
) [static]

isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return true if Op is undef or if its value equal to the specified value.

Definition at line 2055 of file X86ISelLowering.cpp.

References llvm::SDValue::getOpcode(), and llvm::ISD::UNDEF.

Referenced by isCommutedMOVL(), isIdentityMask(), llvm::X86::isMOVDDUPMask(), llvm::X86::isMOVHLPS_v_undef_Mask(), llvm::X86::isMOVHLPSMask(), llvm::X86::isMOVHPMask(), isMOVLMask(), llvm::X86::isMOVLPMask(), llvm::X86::isPSHUFLWMask(), llvm::X86::isSplatLoMask(), llvm::X86::isUNPCKH_v_undef_Mask(), isUNPCKHMask(), llvm::X86::isUNPCKL_v_undef_Mask(), isUNPCKLMask(), ShouldXformToMOVHLPS(), and ShouldXformToMOVLP().

static bool isUndefOrInRange ( SDValue  Op,
unsigned  Low,
unsigned  Hi 
) [static]

isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return true if Op is undef or if its value falls within the specified range (L, H].

Definition at line 2045 of file X86ISelLowering.cpp.

References llvm::SDValue::getOpcode(), and llvm::ISD::UNDEF.

Referenced by isCommutedMOVL(), isCommutedSHUFP(), llvm::X86::isPSHUFLWMask(), and isSHUFPMask().

static bool isUndefShuffle ( SDNode *  N  )  [static]

isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved to an undef.

Definition at line 2764 of file X86ISelLowering.cpp.

References llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ISD::UNDEF, V1, and llvm::ISD::VECTOR_SHUFFLE.

static bool isUNPCKHMask ( SDOperandPtr  Elts,
unsigned  NumElts,
bool  V2IsSplat = false 
) [static]

isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKH.

Definition at line 2280 of file X86ISelLowering.cpp.

References isUndefOrEqual().

Referenced by llvm::X86::isUNPCKHMask().

static bool isUNPCKLMask ( SDOperandPtr  Elts,
unsigned  NumElts,
bool  V2IsSplat = false 
) [static]

isUNPCK